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PRELIMINARY REFERENCE DESIGN PMC - 2001170 ISSUE 1
PM8316 TEMUX-84 PM8611 SBS-LITE
OC-12 LINE CARD REFERENCE DESIGN
PM8316 PM8611
TEMUX-84/SBS-LITE
OC-12 LINE CARD REFERENCE DESIGN
PRELIMINARY ISSUE 1: JUNE 2001
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
PRELIMINARY REFERENCE DESIGN PMC - 2001170 ISSUE 1
PM8316 TEMUX-84 PM8611 SBS-LITE
OC-12 LINE CARD REFERENCE DESIGN
PUBLIC REVISION HISTORY Issue No. 1 Issue Date June 2001 Details of Change Document created.
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PRELIMINARY REFERENCE DESIGN PMC - 2001170 ISSUE 1
PM8316 TEMUX-84 PM8611 SBS-LITE
OC-12 LINE CARD REFERENCE DESIGN
CONTENTS 1 INTRODUCTION...................................................................................... 1 1.1 1.2 1.3 2 3 PURPOSE..................................................................................... 1 SCOPE.......................................................................................... 1 APPLICATION............................................................................... 1
FEATURES .............................................................................................. 3 GENERAL DESCRIPTION....................................................................... 4 3.1 BLOCK DIAGRAM ........................................................................ 4 3.1.1 UPSTREAM DATA FLOW .................................................. 5 3.1.2 DOWNSTREAM DATA FLOW............................................ 9
4
BLOCK DESCRIPTION ......................................................................... 10 4.1 4.2 4.3 4.4 4.5 4.6 4.7 OPTICS ....................................................................................... 10 PM5313 SPECTRA-622.............................................................. 10 PM8316 TEMUX-84 .....................................................................11 PM8611 SBS-LITE ...................................................................... 12 TELECOM BUS INTERFACE ..................................................... 13 SBI BUS INTERFACE ................................................................. 14 MICROPROCESSORS INTERFACE .......................................... 16 4.7.1 COMPACTPCI BRIDGE ................................................... 17 4.7.2 GENERIC ONBOARD PROCESSOR .............................. 18 4.8 4.9 4.10 POWER SUPPLY........................................................................ 19 HOT SWAP ................................................................................. 19 CLOCKS AND OSCILLATORS ................................................... 20
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PRELIMINARY REFERENCE DESIGN PMC - 2001170 ISSUE 1
PM8316 TEMUX-84 PM8611 SBS-LITE
OC-12 LINE CARD REFERENCE DESIGN
5
DESIGN ISSUES ................................................................................... 23 5.1 POWER SUPPLY........................................................................ 23 5.1.1 DECOUPLING .................................................................. 23 5.1.2 POWER-UP SEQUENCE................................................. 23 5.2 5.3 5.4 5.5 5.6 SPECTRA-622 DESIGN CONSIDERATIONS ............................ 24 TEMUX-84 DESIGN CONSIDERATIONS ................................... 24 SBS-LITE DESIGN CONSIDERATIONS..................................... 24 TELECOM AND SBI BUS DESIGN CONSIDERATIONS............ 24 PCI BRIDGE DESIGN CONSIDERATIONS ................................ 25
6
ANALYSIS.............................................................................................. 26 6.1 TIMING........................................................................................ 26 6.1.1 SPECTRA-622 - TEMUX-84 TELECOM BUS INTERFACE .......................................................................................... 26 6.1.2 TEMUX-84 - SBS-LITE SBI336 INTERFACE .................. 29 6.1.3 SPECTRA-622 - PCI9030 INTERFACE .......................... 32 6.1.4 TEMUX-84 - PCI9030 INTERFACE................................. 36 6.1.5 SBS-LITE - PCI9030 INTERFACE................................... 40 6.1.6 XC95288XL CPLD - PCI9030 INTERFACE..................... 41 6.2 POWER ESTIMATE AND THERMAL ANALYSIS........................ 45 6.2.1 TITANIA POWER MODULES ....................................... 46 6.3 SIGNAL INTEGRITY SIMULATIONS .......................................... 46 6.3.1 TELECOM BUS................................................................ 46 6.3.2 SBI336 BUS ..................................................................... 50 6.3.3 MICROPROCESSOR INTERFACE.................................. 54
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PRELIMINARY REFERENCE DESIGN PMC - 2001170 ISSUE 1
PM8316 TEMUX-84 PM8611 SBS-LITE
OC-12 LINE CARD REFERENCE DESIGN
7
DESIGN DETAILS.................................................................................. 60 7.1 7.2 7.3 7.4 7.5 7.6 COMPONENT PLACEMENT ...................................................... 60 LAYER STACKING AND IMPEDANCE CONTROL..................... 61 PCI BUS SIGNAL SPECIFICATION............................................ 62 ROUTING.................................................................................... 63 EMISSION................................................................................... 63 CONNECTORS ........................................................................... 63 7.6.1 COMPACTPCI CONNECTOR .......................................... 63 7.6.2 OC-12 OPTICAL CONNECTOR....................................... 64 7.6.3 HS3 CONNECTOR........................................................... 64 7.6.4 RJ-45 SHIELDED ETHERNET CONNECTOR................. 64 7.6.5 JTAG DEBUG PORT ........................................................ 65 7.6.6 CPLD ISP PORT .............................................................. 65 7.6.7 CPLD CLOCK SMB CONNECTOR .................................. 66 7.6.8 MICTOR CONNECTORS ................................................. 66 7.7 7.8 JUMPER CONFIGURATION....................................................... 66 LEDS ........................................................................................... 68
8
SOFTWARE INTERFACES ................................................................... 70 8.1 8.2 8.3 MEMORY MAP............................................................................ 70 ADDRESS MAPPING ................................................................. 70 CPLD OPERATION..................................................................... 71
9 10 11
DISCLAIMER ......................................................................................... 75 REFERENCES....................................................................................... 76 APPENDIX A: BILL OF MATERIALS ..................................................... 77
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PRELIMINARY REFERENCE DESIGN PMC - 2001170 ISSUE 1
PM8316 TEMUX-84 PM8611 SBS-LITE
OC-12 LINE CARD REFERENCE DESIGN
12 13
APPENDIX B: SCHEMATICS ................................................................ 83 84
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PRELIMINARY REFERENCE DESIGN PMC - 2001170 ISSUE 1
PM8316 TEMUX-84 PM8611 SBS-LITE
OC-12 LINE CARD REFERENCE DESIGN
LIST OF FIGURES FIGURE 1 - SWITCHING SYSTEM ARCHITECTURE ...................................... 2 FIGURE 2 - OC-12 LINE CARD BLOCK DIAGRAM........................................... 4 FIGURE 3 - OC-12 LINE CARD DATA FLOW ................................................... 5 FIGURE 4 - TELECOM BUS DATA FORMAT.................................................... 6 FIGURE 5 - VT1.5 DEMAPPING BY THE TEMUX-84....................................... 7 FIGURE 6 - SBI336 BUS DATA FORMAT ......................................................... 8 FIGURE 7 - SPECTRA-622 TO TEMUX-84 TELECOM BUS INTERFACE ..... 14 FIGURE 8 - TEMUX-84 TO SBS-LITE SBI336 INTERFACE ........................... 16 FIGURE 9 - MICROPROCESSOR INTERFACE TOPOLOGY ........................ 17 FIGURE 10 - EXAMPLE OF A HOT SWAP CIRCUIT....................................... 20 FIGURE 11 - CLOCK DISTRIBUTION.............................................................. 22 FIGURE 12 - TELECOM ADD BUS TIMING DIAGRAM .................................. 26 FIGURE 13 - TELECOM DROP BUS TIMING DIAGRAM ............................... 28 FIGURE 14 - SBI ADD BUS TIMING DIAGRAM.............................................. 29 FIGURE 15 - SBI DROP BUS TIMING DIAGRAM........................................... 31 FIGURE 16 - SPECTRA-622 TO PCI9030 READ ACCESS TIMING DIAGRAM 33 FIGURE 17 - SPECTRA-622 TO PCI9030 WRITE ACCESS TIMING............. 35 FIGURE 18 - TEMUX-84 TO PCI9030 READ ACCESS TIMING DIAGRAM ... 37 FIGURE 19 - PCI9030 TO TEMUX-84 WRITE ACCESS TIMING DIAGRAM .. 39 FIGURE 20 - PCI9030 TO CPLD READ ACCESS TIMING DIAGRAM ........... 41 FIGURE 21 - PCI9030 TO CPLD WRITE ACCESS TIMING DIAGRAM .......... 43 FIGURE 22 - TELECOM ADD BUS SIMULATION........................................... 47
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OC-12 LINE CARD REFERENCE DESIGN
FIGURE 23 - TELECOM DROP BUS SIMULATION........................................ 48 FIGURE 24 - TELECOM BUS CLOCK SIGNAL .............................................. 49 FIGURE 25 - TELECOM ADD BUS DATA SIGNALS....................................... 49 FIGURE 26 - TELECOM DROP BUS DATA SIGNALS .................................... 50 FIGURE 27 - SBI336 DROP BUS SIMULATION ............................................. 51 FIGURE 28 - SBI336 ADD BUS SIMULATION ................................................ 52 FIGURE 29 - SBI336 CLOCK SIGNAL ............................................................ 52 FIGURE 30 - SBI336 DROP BUS WAVEFORM .............................................. 53 FIGURE 31 - SBI336 ADD BUS WAVEFORM................................................. 53 FIGURE 32 - PCI9030 / XC95288XL SIMULATION LAYOUT ......................... 54 FIGURE 33 - PCI9030 / XC95288XL DATA WAVEFORMS ............................. 55 FIGURE 34 - PCI9030 / XC95288XL ADDRESS WAVEFORMS..................... 55 FIGURE 35 - MICROPROCESSOR INTERFACE DATA BUS SIMULATION LAYOUT 56 FIGURE 36 - MICROPROCESSOR DATA BUS, SECTION 1 WAVEFORMS .. 57 FIGURE 37 - MICROPROCESSOR DATA BUS, SECTION 2 WAVEFORMS .. 57 FIGURE 38 - MICROPROCESSOR INTERFACE ADDRESS BUS SIMULATION LAYOUT 58 FIGURE 39 - MICROPROCESSOR ADDRESS BUS WAVEFORMS............... 59 FIGURE 40 - CARD FLOORPLAN .................................................................. 61 FIGURE 41 - LAYER STACK ........................................................................... 62 FIGURE 42 - CPLD LOGIC DIAGRAM WITH PCI9030 ACTIVATED ............... 72
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PRELIMINARY REFERENCE DESIGN PMC - 2001170 ISSUE 1
PM8316 TEMUX-84 PM8611 SBS-LITE
OC-12 LINE CARD REFERENCE DESIGN
LIST OF TABLES TABLE 1 TABLE 2 TABLE 3 TABLE 4 TABLE 5 TABLE 6 TABLE 7 TABLE 8 TABLE 9 PCI9030 LOCAL ADDRESS SPACE ALLOCATION ...................... 18 LOCAL ADDRESS SPACE ALLOCATION ..................................... 19 TELECOM ADD BUS PROPAGATION DELAYS ........................... 27 TELECOM ADD BUS TIMING CONSTRAINTS............................. 27 TELECOM DROP BUS PROPAGATION DELAYS ........................ 28 TELECOM DROP BUS TIMING CONSTRAINTS.......................... 28 SBI ADD BUS PROPAGATION DELAYS....................................... 30 SBI ADD BUS TIMING CONSTRAINTS ........................................ 30 SBI DROP BUS PROPAGATION DELAYS .................................... 32
TABLE 10 SBI DROP BUS TIMING CONSTRAINTS ..................................... 32 TABLE 11 PCI9030 TO SPECTRA-622 READ PROPAGATION DELAYS ..... 34 TABLE 12 PCI9030 TO SPECTRA-622 READ TIMING CONSTRAINTS ....... 34 TABLE 13 PCI9030 TO SPECTRA-622 WRITE PROPAGATION DELAYS.... 36 TABLE 14 PCI9030 TO SPECTRA-622 WRITE TIMING CONSTRAINTS ..... 36 TABLE 15 PCI9030 TO TEMUX-84 READ PROPAGATION DELAYS............ 38 TABLE 16 PCI9030 TO TEMUX-84 READ TIMING CONSTRAINTS ............. 38 TABLE 17 PCI9030 TO TEMUX-84 WRITE PROPAGATION DELAYS .......... 40 TABLE 18 PCI9030 TO TEMUX-84 WRITE TIMING CONSTRAINTS............ 40 TABLE 19 PCI9030 TO XC95288 READ PROPAGATION DELAYS............... 42 TABLE 20 PCI9030 TO XC95288 READ TIMING CONSTRAINTS ................ 42 TABLE 21 PCI9030 TO XC95288 CPLD WRITE PROPAGATION DELAYS .. 44 TABLE 22 PCI9030 TO XC95288 CPLD WRITE TIMING CONSTRAINTS.... 44
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PRELIMINARY REFERENCE DESIGN PMC - 2001170 ISSUE 1
PM8316 TEMUX-84 PM8611 SBS-LITE
OC-12 LINE CARD REFERENCE DESIGN
TABLE 23 POWER CONSUMPTION BY SUPPLY RAIL FOR EACH DEVICE45 TABLE 24 RJ-45 SHIELDED ETHERNET CONNECTOR PIN ASSIGNMENT64 TABLE 25 JTAG DEBUG PORT PIN ASSIGNMENT ...................................... 65 TABLE 26 CPLD ISP PORT PIN ASSIGNMENT ............................................ 66 TABLE 27 OC-12 LINE CARD JUMPER CONFIGURATION.......................... 67 TABLE 28 LED DESCRIPTION ...................................................................... 68 TABLE 29 SYSTEM MEMORY MAP............................................................... 70 TABLE 30 CPLD INTERRUPT STATUS REGISTER ...................................... 73 TABLE 31 SBS-LITE CONTROL REGISTER ................................................. 73 TABLE 32 MAJOR COMPONENTS LIST ....................................................... 77 TABLE 33 BILL OF MATERIALS..................................................................... 77
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PRELIMINARY REFERENCE DESIGN PMC - 2001170 ISSUE 1
PM8316 TEMUX-84 PM8611 SBS-LITE
OC-12 LINE CARD REFERENCE DESIGN
1
INTRODUCTION The OC-12 Line Card Reference Design is a sample application of several PMCSierra devices including: * * * PM5313 SPECTRA-622 PM8316 TEMUX-84 PM8611 SBI Bus Serializer (SBS-Lite)
1.1
Purpose The OC-12 Line Card Reference Design is intended to assist engineers in designing their products using PMC-Sierra's devices. The purpose of this document is to provide a detailed hardware specification for the OC-12 Line Card. The specification detailed here is sufficient to allow design implementation and verification.
1.2
Scope This document describes the design for the OC-12 Line Card. A general description of the card is given, along with a block diagram for the design. A description for each of the functional blocks of the design is given followed by a detailed account of design issues, including physical and mechanical descriptions, timing, simulations and implementation descriptions. The OC-12 Line Card is fully capable of handling either SONET or SDH formats, but for simplicity of explanation, the SONET standard will be dealt with exclusively throughout this document. Please refer to each device datasheet for SDH configuration information.
1.3
Application The OC-12 Line Card is designed to be one of many line cards in a larger switching system. Each line card receives and decodes an OC-12 SONET stream, with the ability to switch any DS0 within the OC-12 frame. The data is then sent over an LVDS serial backplane to the working and protection core cards, which perform switching of the traffic. The core card, using a PM8620 Narrowband Switch Element (NSE-20G), can switch any DS0 from any of the 32 input ports on the core card, to any of the 32 output ports; therefore having the capacity to support a maximum of 16 line cards and 16 link layer cards.
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PRELIMINARY REFERENCE DESIGN PMC - 2001170 ISSUE 1
PM8316 TEMUX-84 PM8611 SBS-LITE
OC-12 LINE CARD REFERENCE DESIGN
When an NSE is placed between the framers of the line cards and link layer devices of the service cards, it allows the construction of an NxDS0 switch of up to 20 Gb/s. Figure 1 demonstrates how up to 16 OC-12 Line Cards can connect to a Core Card to create a switching system with a bandwidth of ~20 Gb/s. Figure 1 - Switching System Architecture
OC-12
Spectra-622 PM5313
4x 4x 4x 4x TEMUX-84 TEMUX-84 TEMUX-84 TEMUX-84 PM8316 PM8610 PM8610 PM8610
SBS-Lite PM8611 OC-12 Line Card
Link Layer Card
SBS PM8610
16 Line Cards
NSE-20G PM8620 Core Card
16 Link Layer Cards
OC-12
Spectra-622 PM5313
4x 4x 4x 4x TEMUX-84 TEMUX-84 TEMUX-84 TEMUX-84 PM8610 PM8610 PM8610 PM8610
SBS-Lite PM8611 OC-12 Line Card
Link Layer Card
The line card is a specific application that demonstrates certain features of the SPECTRA-622, TEMUX-84 and SBS-Lite. Please refer to the individual product datasheets for the full listing of possible applications.
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PRELIMINARY REFERENCE DESIGN PMC - 2001170 ISSUE 1
PM8316 TEMUX-84 PM8611 SBS-LITE
OC-12 LINE CARD REFERENCE DESIGN
2
FEATURES This Reference Design provides the following features: Implements an OC-12 Line Card using the following PMC-Sierra devices: * * * * * * * * * * * * PM5313 SPECTRA-622 OC-12 SONET/SDH payload extractor/aligner PM8316 TEMUX-84 High Density T1/E1 Framer with integrated VT/TU Mapper and M13 Multiplexer PM8611 SBI BUS Serializer (SBS-Lite) 3.3 Volt CMOS telecom bus configured to operate as a 77.76 MHz 8-bit wide telecom bus interface, between the SPECTRA-622 and four TEMUX-84s. Includes a 77.76 MHz 8-bit SBI336 bus, allowing communication between the four TEMUX-84s and the SBS-Lite. Interfaces to a +5V cPCI 33MHZ backplane. Generic onboard processor with ethernet/serial interface Contains oscillators for framing of T1, E1, and DS3 payloads over the Telecom and SBI busses. Provides dual 777.6 MHz Serial SBI336S LVDS links for communication with the core cards over the backplane. Front panel status LED's which displays line status, alarms, and power supply status. Ability to receive 77.76 MHz clock and 2 KHz frame pulse from the backplane, onboard oscillators, or external sources through the front panel. Full Hot Swap Control with extraction indicator.
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PM8316 TEMUX-84 PM8611 SBS-LITE
OC-12 LINE CARD REFERENCE DESIGN
3 3.1
GENERAL DESCRIPTION Block Diagram The OC-12 Line Card is controlled via the CompactPCI bus from a host CPU or a generic processor daughterboard. Figure 2 illustrates the reference design block diagram. Figure 2 - OC-12 Line Card Block Diagram
OC-12 Line
STS-12
Telecom Add
Telecom Drop
77.76 MHz Telecom Bus
Drop Bus Add Bus
Telecom Add
Telecom Drop
Telecom Add
Telecom Drop
Telecom Add
Telecom Drop
Telecom Add
Temux-84 PM8316
Micro I/F Micro I/F SBI Drop SBI Add
Temux-84 PM8316
Micro I/F SBI Drop SBI Add
Temux-84 PM8316
SBI Drop Micro I/F SBI Add
Temux-84 PM8316
SBI Drop SBI Add
Telecom Drop
Drop Bus Add Bus 77.76 MHz SBI Bus
SBI Drop
Micro I/F
SBI Add
Address & Data Bus
I/O
LVDS TX/RX
CPLD XC95288XL
Processor Board
Oscillators A/D
PCI Bridge Primary PCI Bus
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cPCI
5V / 3.3V / 2.5V /1.8V Regulators, Hot-Swap Controller
ETHERNET / SERIAL
A/D A/D
A/D
SBS-Lite PM8611
777.6MHz Serial SBI336S LVDS Bus
A/D
LVDS
LEDS
ODL HP5208
TX/RX I/F Micro I/F
Spectra-622 PM5313
Status Outputs
PRELIMINARY REFERENCE DESIGN PMC - 2001170 ISSUE 1
PM8316 TEMUX-84 PM8611 SBS-LITE
OC-12 LINE CARD REFERENCE DESIGN
A general data flow diagram for the OC-12 Line Card is shown in Figure 3. The following sections describe the receive and transmit data flows. The device functions described here are only a broad overview. Please refer to the product data sheets for a detailed description of each device's functionality. The data flow description for this card uses T1 links as the data being transferred for an example of the capabilities. It supports a mix of T1s, E1s, TVT1.5s, TVT2s, DS3s, E3s, or fractional links. However, each SPE is restricted to carrying a single tributary type. Figure 3 - OC-12 Line Card Data Flow
Line Card SPECTRA-622 SECTION SONET Add SPE's TEMUX-84 SECTION SBI Add SPE's SBS-Lite SECTION Core Card NSE-20G Core Card Switching
SONET OC-12 FRAME
RECEIVE SBI336S
SONET Drop SPE's
SBI Drop SPE's
TRANSMIT SBI336S
OPTICAL INTERFACE
LINE SIDE INTERFACE TELECOM ADD/DROP BUS
SYSTEM SIDE INTERFACE SBI ADD/DROP BUS
SBI336S Bus (LVDS Links)
3.1.1 Upstream Data Flow First, the optical receiver converts the OC-12 signal to an STS-12 electrical signal, and then the SPECTRA-622 recovers the clock from the serial data and converts the serial stream into a parallel format. The SPECTRA-622 processes the section and line overhead of the SONET frame, then extracts the STS-12 Synchronous Payload Envelope. The SPECTRA-622 is configured to extract the STS-12 payload from the receive stream and output it onto the 8-bit wide telecom drop bus. Each TEMUX-84 processes one STS-3 payload transmitted over the telecom bus by the SPECTRA-622. Figure 4 shows how the data is formatted as it is sent over the Telecom bus.
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OC-12 LINE CARD REFERENCE DESIGN
Figure 4 - Telecom Bus Data Format
1 36 1080 columns
9 Rows
Transport Overhead
STS-12 Envelope Capacity
36 37 -First Number indicates STS-3 # -Second Number indicates STS-1 SPE# -Third Number indicates STS-1 Four STS-3 payloads* column # Transported Across Telecom Bus One STS-3 payload is processed by one of the four TEMUX-84 devices
1080
2,3,87
3,3,87
STS-12 Byte Interleaved Payload Order
1,3,87
* Each STS-1 Payload
consists of 1 SPE
Each TEMUX-84 demaps 84 SONET VT1.5 streams from one STS-3 payload. The VT1.5 structuring within the SPE is shown in Figure 5. After each T1 link is extracted from its respective VT1.5, the TEMUX-84 can frame to the common DS1 signal formats (SF, ESF) on each T1 link, or the framing can be bypassed in unframed mode. Each T1 framer supports performance monitoring and is independently software configurable. The host processor can access any T1 framer or transmitter on any of the TEMUX-84 devices.
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4,3,87
1,1,1
2,1,1
3,1,1
4,1,1
1,2,1
2,2,1
3,2,1
4,2,1
1,3,1
2,3,1
3,3,1
4,3,1
PRELIMINARY REFERENCE DESIGN PMC - 2001170 ISSUE 1
PM8316 TEMUX-84 PM8611 SBS-LITE
OC-12 LINE CARD REFERENCE DESIGN
Figure 5 - VT1.5 Demapping by the TEMUX-84
1 261
Tributary Pointers 4 x STS-3 payloads
J1 J1 J1 BBB C2 C2 C2 9 Rows GGG F2 F2 F2 HHH Z3 Z3 Z3 Z4 Z4 Z4 Z5 Z5 Z5
RRR RRR RRR RRR
RRR RRR RRR RRR
VT 1.5 #1 VT 1.5 #28
VT VT VT VT 1.5 1.5 1.5 1.5 #1 #1 #1 #2
VT 1.5 #28
RRR RRR RRR RRR RRR
RRR RRR RRR RRR RRR
VT 1.5 #1
VT 1.5 #28
Path Overhead SPE#1 SPE#3 SPE#1-3 per SPE#2 SPE#1 STS-1 DS0#1,4,7,...22 DS0#2,5,8,...23 DS0#3,6,9,...24
SPE#3
SPE#1
SPE#3
SPE#1
SPE#3
Each T1 is then byte-interleaved onto the SBI bus in the format shown in Figure 6. Note that the format used in the figure is representative of T1 streams being sent on the SBI bus. The format is slightly different for other data structures. For example, when sending DS3 or E3 data, SBI columns 60-72 are used.
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Figure 6 - SBI336 Bus Data Format
1 25
C1
72 73
V1 1 4 7 10 13 16 19 22 V1 1 4 7 10 13 16 19 22 V1 1 4 7 10 13 16 19 22 V1 1 4 7 10 13 16 19 22 V1 1 4 7 10 13 16 19 22
409
V5 2 5 8 11 14 17 20 23 V5 2 5 8 11 14 17 20 23
1080
CAS CAS 3 3 6 6 9 9 12 12 15 15 18 18 21 21 24 24
Unused
9 Rows 0
Unused TEMUX#1 SPE#1 T1#1
Unused
TEMUX#2 TEMUX#4 SPE#1 SPE#1 T1#1 T1#1
TEMUX#1-4 SPE#1-3 T1#2-28
TEMUX#3 TEMUX#1 SPE#1 SPE#2 T1#1 T1#1 V1 DS0#1 DS0#4 DS0#7 DS0#10 DS0#13 DS0#16 DS0#19 DS0#22
TEMUX#1 TEMUX#1-4 SPE#1 SPE#1-3 T1#1 T1#2-28 TEMUX#2 SPE#1 T1#1 V1 DS0#1 DS0#4 DS0#19 DS0#10 DS0#13 DS0#16 DS0#7 DS0#22
TEMUX#3 SPE#3 T1#28 TEMUX#4 SPE#3 T1#28
As the SBI336 bus is sent through the SBS, the Memory Switch Unit allows any DS0 to be swapped with any other DS0 within the STS-12 frame.
As the SBS-Lite receives the data from the SBI Bus, it reads each DS0 into the Incoming Memory Switch Unit (IMSU). The Incoming Memory Switch Unit (IMSU) block has two connection memory pages and two data pages. The connection memory pages controls where each byte is switched and the alternating data pages fill up with one frame (9720 bytes) of data. The active page of the connection memory is controlled by the ICMP. When set to high, page 1 of the connection memory is active and when set to low, page 0 is active. The IMSU allows access to all DS0s within the STS-12 frame, so any DS0 can be swapped with any other DS0 within that frame. The ICMP signal is controlled by the XC95288XL CPLD on the line card. In this system, the CPLD re-routes the ICMP signal received from the backplane or generates a signal depending on the values set in the SBS-Lite registers. The data is then encoded using the 8B/10B format and is sent, using LVDS, over the backplane to a link layer device.
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OC-12 LINE CARD REFERENCE DESIGN
3.1.2 Downstream Data Flow For this section of the data flow description, please refer to Figure 4 through Figure 6 for details. In the downstream direction, the SBS-lite receives SBI336S data from the NSE via the backplane LVDS interface. The SBI336S data is decoded from 8B/10B format and then written into the OMSU of the SBS. The Outgoing Memory Switch Unit (OMSU) block has two connection memory pages and two data pages. The connection memory pages controls where each byte is switched and the alternating data pages fill up with one frame (9720 bytes) of data. The active page of the connection memory is controlled by the OCMP, which is generated by the CPLD or received from the backplane. When set to high, page 1 of the connection memory is active and when set to low, page 0 is active. Each TEMUX-84 reads data from the SBI336 bus once every four SREFCLK cycles. When the TEMUX-84 is receiving data from the SBI336 bus, it uses the SAJUST_REQ signal to speed up, slow down, or maintain the rate at which the data is being transmitted. The SBS-Lite receives the JUST_REQ signal and passes it on to the link layer device, which appropriately changes the data rate. Each TEMUX-84 processes the incoming data, recovering T1 clock and data for up to 84 links in framed or unframed mode. Please refer to Section 4.3 for a detailed description of the various framing formats that the TEMUX-84 supports. Each of the tributaries is then byte interleaved and sent to the SPECTRA-622 via the Telecom ADD Bus. The SPECTRA-622 interprets the pointers bytes from all of the received STS-3s, then the path overhead from each SPE is processed. All four STS-3 payloads are then aligned to the frame of the transmit stream. The data is transformed into an STS-12 payload format. Line and the Path overhead are added to the payload to create a full STS-12 frame, which is mapped to the system timing reference. The full SONET STS-12 frame is then transmitted to the optical interface unit. The transmitted signal is then converted to an OC-12 stream or optical format by the Optical Interface unit.
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PM8316 TEMUX-84 PM8611 SBS-LITE
OC-12 LINE CARD REFERENCE DESIGN
4 4.1
BLOCK DESCRIPTION Optics The HP HFCT-5208 optical transceiver performs the conversion between the optical OC-12 signal and the electrical STS-12 signal.
4.2
PM5313 SPECTRA-622 The PM5313 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER (SPECTRA-622) terminates the transport and path overhead of STS-12 (STM-4/AU3 or STM4/AU4) and STS-12c (STM-4-4c) streams at 622.08 Mbit/s. The SPECTRA-622 implements significant functions for a SONET/SDH compliant line interface, as well as DS3 mapping. The SPECTRA-622 receives SONET/SDH frames via a bit serial interface, recovers clock and data, and terminates the SONET/SDH section (regenerator section), line (multiplexer section), and path. It performs framing (A1, A2), descrambling, detects alarm conditions, and monitors section and line bit interleaved parity (BIP) (B1, B2), accumulating error counts at each level for performance monitoring purposes. B2 errors are also monitored to detect signal fail and signal degrade threshold crossing alarms. Line remote error indications (M1) are also accumulated. A 16 or 64 byte section trace (J0) message may be buffered and compared against an expected message. In addition, the SPECTRA-622 interprets the received payload pointers (H1, H2), detects path alarm conditions, detects and accumulates path BIPs (B3), monitors and accumulates path Remote Error Indications (REIs), accumulates and compares the 16 or 64 byte path trace (J1) message against an expected result and extracts the synchronous payload envelope (virtual container). All transport and path overhead bytes are extracted and serialized on lower rate interfaces, allowing additional external processing of overhead, if desired. The extracted SPE (VC) is placed on a Telecom DROP bus. In Telecombus applications, frequency offsets (e.g., due to plesiochronous network boundaries, or the loss of a primary reference timing source) and phase differences (due to normal network operation) between the received data stream and the DROP bus are accommodated by pointer adjustments in the DROP bus. The SPECTRA-622 transmits SONET/SDH frames, via a bit serial interface, and formats section (regenerator section), line (multiplexer section), and path overhead appropriately. The SPECTRA-622 provides transmit path origination for a SONET/SDH STS-12 (STM-4/AU3 or STM-4/AU4) or STS-12c (STM-4-4c) stream. It performs framing pattern insertion (A1, A2), scrambling, alarm signal
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PM8316 TEMUX-84 PM8611 SBS-LITE
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insertion, and creates section and line BIPs (B1, B2) as required to allow performance monitoring at the far end. Line remote error indications (M1) are optionally inserted. A 16 or 64 byte section trace (J0) message may be inserted. In addition, the SPECTRA-622 generates the transmit payload pointers (H1, H2), creates and inserts the path BIP, optionally inserts a 16 or 64 byte path trace (J1) message, optionally inserts the path status byte (G1). In addition to its basic processing of the transmit SONET/SDH overhead, the SPECTRA-622 provides convenient access to all overhead bytes, which are inserted serially on lower rate interfaces, allowing additional external sourcing of overhead, if desired. The SPECTRA-622 also supports the insertion of a large variety of errors into the transmit stream, such as framing pattern errors and BIP errors, which are useful for system diagnostics and tester applications. On the OC-12 Line Card, the inserted SPE (VC) is sourced from a Telecombus ADD stream. For Telecombus applications, the SPECTRA-622 maps the SPE from a Telecom ADD bus into the transmit stream. Frequency offsets (e.g., due to plesiochronous network boundaries, or the loss of a primary reference timing source) and phase differences (due to normal network operation) between the transmit data stream and the ADD bus are accommodated by pointer adjustments in the transmit stream. The SPECTRA-622 supports Time-Slot Interchange (TSI) on the Telecom ADD and DROP buses. On the DROP side, the TSI views the receive stream as twelve independent time-division multiplexed columns of data (i.e. twelve constituent STS-1 (STM-0/AU3) or equivalent streams or time-slots or columns). Any column can be connected to any time-slot on the DROP bus. Both column swapping and broadcast are supported. Time-Slot Interchange is independent of the underlying payload mapping formats. Similarly, on the ADD side, data from the ADD bus is treated as twelve independent time-division multiplexed columns. Assignment of data columns to transmit time-slots (STS-1 (STM-0/AU3) or equivalent streams) is arbitrary. The SPECTRA-622 is implemented in low power, +3.3 Volt, CMOS technology. It has TTL and pseudo ECL (PECL) compatible inputs and outputs and is packaged in a 520 pin SBGA package. 4.3 PM8316 TEMUX-84 The High Density T1/E1 Framer with Integrated VT/TU Mappers and M13 Multiplexers (TEMUX-84) supports asynchronous multiplexing (demultiplexing) of 84 DS1s into (out of) three DS3 signals. In the ingress direction, each of the 84 T1 links is either demultiplexed from a channelized DS3 or extracted from SONET VT1.5, TU-11 or TU-12 telecom mapped bus. Each T1 framer can be configured to frame to the common DS1
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PM8316 TEMUX-84 PM8611 SBS-LITE
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signal formats (SF, ESF) or to be bypassed (unframed mode). Each T1 framer detects and indicates the presence of Yellow and AIS patterns and also integrates Yellow, Red, and AIS alarms. In the egress direction, framing is generated for 84 T1s into either a DS3 multiplex or a SONET/SDH mapped add bus. Each T1 transmitter frames to SF or ESF DS1 formats, or framing can be optionally disabled. The TEMUX-84 supports signaling insertion, idle code substitution, data insertion, line loopback, data inversion and zero-code suppression on a per-DS0 basis. PRBS generation or detection is supported on a framed and unframed T1 basis. A Scaleable Bandwidth Interconnect (SBI) high density byte serial system interface provides higher levels of integration and dense interconnect. The SBI bus interconnects up to 84 T1s or 63 E1 EITHER synchronously or asynchronously. The SBI allows transmit timing to be mastered by either the TEMUX-84 or link layer device connected to the SBI bus. In addition to framed T1s and E1s, the TEMUX-84 can transport unframed T1 or E1 links and framed or unframed DS3 or E3 links over the SBI bus. This reference design utilizes a byte wide SBI bus running at 77.76 MHz. 4.4 PM8611 SBS-Lite The PM8611 SBI336 Bus Serializer (SBS-Lite) is a monolithic integrated circuit that implements conversion between byte-serial 77.76 MHz SBI336 bus and redundant 777.6 Mbps bit-serial LVDS links. In SBI bus mode the SBS-Lite implements conversion between 77.76 MHz SBI336 bus format and redundant 777.6 Mbps bit-serial 8B/10B-base serial SBI336S bus format. In line with the bus conversion is a DS0 granular switch allowing any input DS0 to be output on any output DS0. The SBS-Lite can be used to connect and switch high density T1/E1 framer devices supporting an SBI bus with link layer devices supporting an SBI bus over a serial backplane. Putting the Narrowband Switch Element, NSE, between the framer and link layer devices allows construction of up to 20Gb/s NxDS0 switches. In the ingress direction, the SBS-lite connects an incoming 77.76MHz SBI336 stream to a pair of redundant serial SBI336S LVDS links through a DS0 memory switch. In telecom bus mode an incoming 77.76MHz telecom bus that has the J1 path fixed and all high order pointer justifications converted to tributary pointer justifications can be switched through a VT granular switch to a pair of redundant serial LVDS telecom bus format links. The incoming data is encoded into an extended set of 8B/10B characters and transferred onto two redundant 777.6 Mbps serial LVDS links. SBI or telecom bus frame boundaries, pointer justification events and master timing controls are marked by 8B/10B control
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PM8316 TEMUX-84 PM8611 SBS-LITE
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characters. Incoming SPEs may be optionally overwritten with the locally generated X23 + X18 + 1 PRBS pattern for diagnosis of downstream equipment. The PRBS processor is configurable to handle any combination of SPEs and can be inserted independently into either of the redundant LVDS links. A DS0 memory switch provides arbitrary mapping of streams on the incoming SBI336 bus stream to the working and protect LVDS links at DS0 granularity. In telecom bus mode a VT1.5/VT2 memory switch provides arbitrary mapping of tributaries on the incoming telecom bus stream to the working and protect LVDS links. Multi-cast is supported. In the egress direction, the SBS-lite connects two independent 777.6 Mbps serial LVDS links to an outgoing SBI336 Bus. Each link contains a constituent SBI336S stream. Bytes on the links are carried as 8B/10B characters. The SBS-lite decodes the characters into data and control signals for a single 77.76MHz SBI336 bus. Alternatively the SBS-lite decodes two independent 777.6 Mbps telecom bus formatted serial LVDS links characters into a single 77.76MHz telecom bus. A pseudo-random bit sequence (PRBS) processor is provided to monitor the decoded payload for the X23 + X18 + 1 pattern in each SPE. The PRBS processor is configurable to handle any combination of SPEs in the serial LVDS link. Data on the outgoing SBI336 bus stream may be sourced from either of the LVDS links. An In-band signaling link over the serial LVDS links allows this device to be controlled by a companion switching device, the Narrowband Switching Element, NSE20G. This link can be used as communication link between a central processor and the local microprocessor. 4.5 Telecom Bus Interface The Telecom bus consists of an 8-bit wide interface that transports data between the SPECTRA-622 and the TEMUX-84 devices. In this application, the telecom bus runs at 77.76 MHz. The data is in the form of four interleaved STS-3 Payloads while on the bus, as show in Figure 4. Each TEMUX-84 has an 8-bit wide Telecom bus interface and receives one of the four STS-3 payloads from the SPECTRA-622. Only one TEMUX-84 needs to drive the LAC1J1V1 signal to the SPECTRA-622. All other TEMUX-84s must be configured via the TXPTR[9:0] bits, in the SONET/SDH Transmit Pointer Configuration Register, to use the same J1 offset. A 77.76 MHz reference clock supplies the system clock for the bus. The LAC1 and DFP signals are generated by the CPLD.
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Figure 7 - SPECTRA-622 to TEMUX-84 Telecom Bus Interface
TEMUX-84 #1 Telecom Bus Section SPECTRA-622 Telecom Bus Section
DC1J1V1[0] DD[7:0] DDP[0] DPL[0] DC1J1V1[1] DD[15:8] DDP[1] DPL[1] DC1J1V1[2] DD[23:16] DDP[2] DPL[2] DC1J1V1[3] DD[31:24] DDP[3] DPL[3] LAC1 LAC1J1V1 LADATA[7:0] LADP LAPL LDC1J1V1 LDDATA[7:0] LDDP LDPL
TEMUX-84 #2 Telecom Bus Section
N/C LAC1 LAC1J1V1 LADATA[7:0] LADP LAPL LDC1J1V1 LDDATA[7:0] LDDP LDPL
AC1J1V1/AFP[0] AD[7:0] ADP[0] APL[0] AC1J1V1/AFP[1] AD[15:8] ADP[1] APL[1] AC1J1V1/AFP[2] AD[23:16] ADP[2] APL[2] AC1J1V1/AFP[3] AD[31:24] ADP[3] APL[3]
TEMUX-84 #3 Telecom Bus Section
N/C LAC1 LAC1J1V1 LADATA[7:0] LADP LAPL LDC1J1V1 LDDATA[7:0] LDDP LDPL
Telecom ADD BUS
TelecomDROP BUS
TEMUX-84 #4 Telecom Bus Section
N/C LAC1 LAC1J1V1 LADATA[7:0] LADP LAPL LDC1J1V1 LDDATA[7:0] LDDP LDPL *N/C = Not Connected
77.76 MHz Telecom Bus
4.6
SBI Bus Interface The Scaleable Bandwidth Interconnect (SBI) bus provides an interface for the interconnection of asynchronous and synchronous multi-port physical interface devices with multi-channel and multi-function link layer devices. The OC-12 Line Card implements a SBI336 bus configuration. The bus will run at 77.76 MHz and is exactly four 19.44 MHz SBI buses byte-interleaved together. Since each device on the bus has its own timeslot, no capabilities for bus collision detection are required.
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PM8316 TEMUX-84 PM8611 SBS-LITE
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The I/O SDC1FP signal is used to indicate SBI bus multiframe alignment. The signal is supplied to the drop bus by the CPLD, rather than the TEMUX-84s directly driving this signal. The OC1FP[1] signal from the SBS-Lite drives the SAC1FP signal. This signal also indicates the multiframe alignment which occurs every 4 frames, therefore this signal is pulsed every fourth octet to produce a 2kHz multiframe signal. See Section 4.10 for further details regarding frame pulses. See Figure 8 for a detailed diagram of the connections between the TEMUX-84s and SBS-Lite.
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Figure 8 - TEMUX-84 to SBS-Lite SBI336 Interface
TEMUX-84 SBI Section 3.3V
CTCLK SREFCLK S77
SBI336 ADD BUS
SBI336 DROP BUS
SAC1FP SADATA[7:0] SADP SAV5 SAPL SADJUST_REQ SDC1FP SDDATA[7:0] SDDP SDV5 SDPL
Ref. Clock Source
77.76 MHz 8 kHz
TEMUX-84 SBI Section
3.3V
CTCLK SREFCLK S77
SAC1FP SADATA[7:0] SADP SAV5 SAPL SADJUST_REQ SDC1FP SDDATA[7:0] SDDP SDV5 SDPL
SBS-Lite SBI Section
IC1FP IDATA[7:0] IDP IV5 IPL SREFCLK77 JUST_REQ OC1FP ODATA[7:0] ODP OV5 OPL
TEMUX-84 SBI Section
3.3V
CTCLK SREFCLK S77
SAC1FP SADATA[7:0] SADP SAV5 SAPL SADJUST_REQ SDC1FP SDDATA[7:0] SDDP SDV5 SDPL
TEMUX-84 SBI Section
3.3V
CTCLK SREFCLK S77
SAC1FP SADATA[7:0] SADP SAV5 SAPL SADJUST_REQ SDC1FP SDDATA[7:0] SDDP SDV5 SDPL
4.7
Microprocessors Interface The board has been designed with two possible processor interfaces. One is an external processor that uses a PCI Bridge to access devices and the other is an onboard generic processor. The OC-12 Line Card switches between the two interfaces by setting a specified pin on the CPLD to either a logic high or low.
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Set the pin to high when using the PCI Bridge interface and low when using the generic processor interface. See Table 27 for detailed pin settings. Figure 9 demonstrates the board architecture. Figure 9 - Microprocessor Interface Topology
RES
1 2 PCI Bridge ADDRP<17..0> DATAP<15..0> CPLD XC95288XL ADDRN<17..0> DATAN<15..0> Generic Processor Board
Jumper setting determines which processor is used.
Temux-84 PM8316
Temux-84 PM8316
Temux-84 PM8316
Temux-84 PM8316
ADDR_B<12..0> DATA_B<7..0>
Spectra-622 PM5313
SBS-Lite PM8611
ADDR_A<13..0> DATA_A<15..0>
4.7.1 CompactPCI Bridge The host processor will access the devices on the line card via the CompactPCI interface. The card uses a PCI Bridge and various decode logic inside a CPLD so that all registers on each of the devices are accessible. The PCI Bridge used is the PLX Technology PCI9030 PCI Bus Target Interface Chip. The PCI9030 provides a target only interface, and as such does not initiate PCI bus transactions. Not all of the devices on the microprocessor bus have sufficient output drive to properly drive the bus. Therefore the CPLD creates two individual Data and Address buses, effectively splitting the bus into two sections. This split allows each device to correctly drive their section of the bus. Figure 9 above shows an overview of the bus topology.
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PM8316 TEMUX-84 PM8611 SBS-LITE
OC-12 LINE CARD REFERENCE DESIGN
The PCI9030 is configured for single read/write operation. Burst read/write operation is not supported by any devices on the line card. The local address space is configured to be 32-bit non-multiplexed, big endian, and nonprefetchable. Although most devices on the line card have only an 8-bit or 16-bit data bus, the PCI9030 is configured to use a 32-bit data bus. This was done to simplify the hardware design. Prefetching is not possible in this application because the line card has a number of registers with read side affects (e.g. interrupt status registers). The local bus is clocked at 33MHz by looping the buffered PCI clock output (BCLKO) available from the PCI9030 back to the local bus clock input. The PCI9030 is 5V tolerant, so there is no need for level conversion when accessing a 5V PCI bus. The local address spaces are allocated in the following fashion: Table 1 PCI9030 Local Address Space Allocation Function Spectra-622 TEMUX-84 (CPLD will decode addresses for each) SBS-Lite CPLD internal registers
Address Space 0 1 2 3
Please refer to the PCI9030 datasheet [4] for more information. 4.7.1.1 SEEP The NM93CS56 Serial EEPROM from National Semiconductor is used to store configuration information for the PCI9030 Bridge. This specific SEEP (or equivalent) is required by PCI9030 because it supports sequential read operations. Refer to the PCI9030 datasheet [4] for information on the format of the configuration data stored in the SEEP. 4.7.2 Generic Onboard Processor The OC12 Line Card is equipped with a generic onboard processor can be used to provide read and write operations. The local processor bus allows direct connection to memory and peripheral devices. The generic processor must provide the following minimum requirements:
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* * * * *
18 bit address bus and a 16 bit data bus Two chip selects. The CPLD will further decode the address bits so the microprocessor can individually read and write from any device. Runs from either a 3.3V and/or 1.8 V source. Single interrupt line. An Ethernet or serial interface to allow direct access to the onboard processor from an host computer.
As in the case of the PCI9030, the microprocessor bus does not have sufficient output drive to properly drive the bus to each device. Therefore the Address and Data signals are driven twice by the CPLD, effectively splitting up the bus. Figure 9 shows an overview of the bus topology. A generic processor with two chip select lines would allocate the local address spaces in the following fashion: Table 2 Local Address Space Allocation Function Spectra-622, SBS-Lite TEMUX-84 (1,2,3 & 4)
Address Space CS0 CS1
Further decoding is required by the CPLD in order to target each individual device. 4.8 Power Supply The OC-12 Line Card reference design contains components that operate at 1.8V and 3.3V, referenced to ground. The 5V and 3.3V supplies are provided to the board through the CompactPCI connector from the backplane. The 1.8V and 3.3V supplies are generated from onboard power modules. 4.9 Hot Swap The Line Card has been designed to be hot-swap compatible. The Hot Swap Specification [2] says - "The basic purpose of the Hot Swap addition to CompactPCI is to allow the orderly insertion and extraction of boards without adversely affecting system operation."
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The Line Card employs a hot swap compatible cPCI bridge, PLX PCI9030, and a hot swap controller, the Linear Technology LTC1422. The cPCI connector is assembled with three different length pins, as required by the hot swap specification [2]. An example of the hot swap circuit is shown in Figure 10 below. Figure 10 - Example of a Hot Swap Circuit
+ 1.8 V
CompactPCI Connector
+3.3V +5V VIO_Long
0.005 QC
+ 5V
TPM
3.3V - 1.8V
+ 3.3V QD
TPM
5V - 3.3V
6K81
10 10K
10 1M 0.047uF 0.022uF
LTC1422
4K7 4K7 4K7 BD_SEL# QA SENSE VCC ON TIMER 0.33uF FB GATE RESET 2K43
GND Shortest GND Longest
To Reset Circuit
4.10
Clocks and Oscillators A 77.76 MHz 20ppm PECL oscillator is required on the card to drive the SPECTRA-622 receive section. A 37.056 MHz 32ppm oscillator is required on the card to drive the digital phase locked loop on the TEMUX-84s that perform jitter attenuation on the T1 recovered clocks. A 51.84 MHz 50ppm oscillator is required on the TEMUX-84s to generate a gapped DS3 clock when demapping a DS3 from the SONET stream and for receiving a DS3 from the SBI bus interface. A 44.736 MHz 32ppm oscillator is required for mapping of DS3s onto the Telecom Bus. A 49.152 MHz 32ppm oscillator is required on the card to drive the digital phase locked loop on the TEMUX-84s that perform jitter attenuation on the E1 recovered clocks.
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A 77.76 MHz clock will be used to drive the SBI336 Bus and the Telecom bus. The clock must have between 40%-60% duty cycle. The CPLD will also divide this signal by 9720 to generate the 8 kHz synchronization pulse (CTCLK) and other framing pulses. From the onboard oscillators the CTCLK signal is then divided by 4 to generate the 2 kHz synchronization pulses (DFP/LAC1) and other framing pulses. The 77.76 MHz can be attained from the following three sources. * * * Backplane reference clock. Local clock source. External clock source.
All three 77.76 MHz sources are fed into the CPLD. The CPLD has jumpers that are set to one of the sources. As the 77.76 MHz reference clock, the board can attain a 2 kHz framing pulse from the same three sources listed above. All three 2 kHz sources are fed into the CPLD. The CPLD has jumpers that are set to one of the sources. See Table 27 for details on the CPLD pin settings. The two SMB connector that are connected to the CPLD are used for receiving synchronization or clock signals from an external source. The OC-12 line card can receive a 77.76 MHz clock and a 2 kHz frame pulse from an external source. Most clocks that are connected to more than one device are fed through a clock buffering device. The OC-12 Line Card uses several Pericom PI49FCT3805 clock buffers, combined with series termination resistors, to ensure that a clean, fast clock signal is provided to all devices. A diagram showing the major clock distribution networks on the card are shown below in Figure 11.
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Figure 11 - Clock Distribution
LOC_77M BP_FP BP_77M
77.76MHz
BackPlane 2 KHz Frame Pulse
CPLD XC95288XL
77M SOURCE CTCLK LAC1 DFP FP
2 kHz 2 kHz 8 kHz
77.76 MHz
BackPlane 77.76 MHz System Clock
2 kHz
Buffer
SREFCLK
LREFCLK
2
Spectra-622 PM5313
77.76 MHz
77.76 MHz
SMB Inputs External 77.76MHz clock and 2KHz FP
33.33 MHz
CLOCK
TEL_CLK
77.76 MHz
LCLK
25 MHz
51.84MHz
37.056MHz
44.736MHz
Buffer
Buffer
Buffer
5 4 44 12
4
PLX PCI9030
Generic Processor Board
4
4
PCI_CLK
33.33 MHz (from cPCI Bus)
SBS-Lite PM8611
Temux-84 Temux-84 Temux-84 PM8316 Temux-84 PM8516 PM8516 PM8516
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5 5.1
DESIGN ISSUES Power Supply
5.1.1 Decoupling The power modules used require proper input and output decoupling. Refer to section 6.2.1 for details about the Power Module. The analog power supply pins require a filtering network between the ground plane and the power plane. This filtering method should be used when supplying analog power to both 1.8V and 3.3V devices. Please refer to Appendix A: Bill of Materials for component values. 5.1.2 Power-Up Sequence The power up sequence must be adhered to, otherwise device latch-up can occur. The power supplies must turn on in the following sequence: 1. 5V Power 2. 3.3V Digital Power 3. 3.3V Analog Power 4. 1.8V Digital Power 5. 1.8V Analog Power The power down of the card must be performed in the reverse sequence. The delaying of the 1.8V digital power versus the 3.3V digital power is the critical factor since 1.8V is the core supply voltage for some of the devices and must come up after the 3.3V I/O supply voltage. The delaying of analog supplies to come up after its digital counterpart is easily accomplished by the analog supply filtering components. Since it takes time to charge the filter capacitors, the charging delays the analog supply rail a reasonable amount of time for the digital power to stabilize. If the simple solution of a filtering network cannot be implemented, then the analog power pins should be current limited to the maximum latch-up current of 100mA while the digital power stabilizes.
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5.2
SPECTRA-622 Design Considerations Provide separate +3.3V analog transmit, +3.3V analog receive, and +3.3V digital supplies. Connect the supplies together at one point close to the +3.3V output of the power supply. High-frequency decoupling capacitors are required to prevent the transmitter from coupling noise into the receiver and to prevent transients from coupling into the reference circuitry. BIAS voltages (VBIAS and PBIAS) must be applied before VDD or simultaneously with VDD to prevent current flow through the ESD protection devices that exist between BIAS and VDD power supplies.
5.3
TEMUX-84 Design Considerations The clock signals XCLK_T1 and DS3_REF signals must be carefully routed from the clock buffers to the TEMUX-84 parts. The lines should be properly terminated and should not run near any of the data busses if possible.
5.4
SBS-Lite Design Considerations The SBS-Lite should be placed so that there are no major components between the SBS-Lite and the backplane connector. The LVDS links should be able to be routed in the shortest distance possible to the backplane. The length of the traces in each of the LVDS line pairs should be matched in order to minimize skew. Skew between the signals of a pair means a phase difference between signal. This destroys the magnetic field cancellation and results in EMI. Therefore the pair lengths should be matched within 100 mils.
5.5
Telecom and SBI Bus Design Considerations Each signal on the busses requires adequate termination to prevent reflections. At each point where a bus line connects to a driving device, a series resistor should be placed on the line. The value should be large enough to reduce ringing and reflections, but not too large, as it would impair the drive capability of the output. The MICTOR connectors that are used to monitor the signals on these busses should be placed in such a way to minimize trace length between all points on the bus. However, the spacing around the connectors must allow for the special MICTOR pin adapter boards to be plugged in without physical interference between adjacent connectors.
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PM8316 TEMUX-84 PM8611 SBS-LITE
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Any multipoint bus that has tristate ability should have pull-up resistors to avoid the bus floating to unknown levels when not being driven. A suitable pull-up value is 10K. On the OC-12 Line Card both the Telecom bus and SBI bus run at 77.76 MHz 8bit busses. 5.6 PCI Bridge Design Considerations During power up, the PCI RST# signal resets the default values of the PCI 9030 internal registers. In return, the PCI 9030 outputs the local reset signal (LRESET#) and checks for the existence of the serial EEPROM. If a serial EEPROM is installed, and the first 16-bit word is not FFFF, the PCI 9030 initializes the internal registers from the serial EEPROM. Otherwise, default values are used. The PCI 9030 configuration registers can only be written by the optional serial EEPROM or the PCI host processor. During the serial EEPROM initialization, the PCI 9030 response to PCI target accesses is RETRYs.
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6 6.1
ANALYSIS Timing In the timing analysis figures of this section, a gray waveform indicates uncertainty, and a black waveform indicates an input that is not valid since more than one device may be driving the signal at that time. All times are measured in nanoseconds. (ns)
6.1.1 SPECTRA-622 - TEMUX-84 Telecom Bus Interface The telecom bus is a synchronous interface that carries SPE data between the SPECTRA-622 and the four TEMUX-84 devices. The telecom bus is synchronized to a 77.76 MHz clock source. The AC1J1V1 signal is sampled on the rising edge of LREFCLK and indicates frame, payload and tributary multiframe boundaries. See Figure 12 below for a diagram of the Telecom Add bus timing and Figure 13 for the drop bus timing. Figure 12 - Telecom ADD Bus Timing Diagram
0ns T1 T2 25ns T3 T4 50ns
ACK, LREFCLK tS AC1 tP TEL tH AC1 AC1J1V1 tP TEL temux#1 tP TEL temux#2 tP TEL temux#3 tP TEL temux#4 tS AD tH AD tZ tS AD tH AD tZ TEL tS AD tH AD tZ TEL tS AD tH AD tZ TEL tS AC1 tP TEL tH AC1 tS AC1 tP TEL tH AC1 tS AC1 tP TEL tH AC1 tP TEL tH AC1
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In reference to Figure 12, the sequence of events for one Telecom ADD bus clock cycle is as follows: 1. On the rising edge of LREFCLK, at the start of T1, the first TEMUX-84 drives valid data onto the Telecom Add bus after the propagation delay tP TEL. 2. On the rising edge of LREFCLK, at the start of T2, the SPECTRA-622 samples the data from the Telecom Add bus and the first TEMUX-84 has a delay of tZ TEL before tristating. All Telecom Add bus signals require that the bus data be valid during setup time, tS AD, and hold time, tH AD. Also at the start of T2, TEMUX-84 #2 drops valid data onto the Telecom Add bus. 3. At the start of T3, TEMUX-84 #3 uses the Telecom Add bus and at the start of T4, TEMUX-84 #4 uses the Telecom Add bus. The cycle repeats with each TEMUX-84. The output propagation delays involved in Figure 12 are shown in the following table: Table 3
Name tP TEL tZ TEL
Telecom Add Bus Propagation Delays
Device TEMUX-84 TEMUX-84 Description LREFCLK to TEMUX-84 Outputs going Valid from Tristate Time to Data tristating again Min 1 1 Max 6 5
The input constraints involved in Figure 12 are shown in the following table: Table 4
Name tS AC1 tS AD tH AC1 tH AD
Telecom Add Bus Timing Constraints
Device SPECTRA-622 SPECTRA-622 SPECTRA-622 SPECTRA-622 Description Telecom Bus Set-up Time Telecom Bus Set-up Time Telecom Bus Hold Time Telecom Bus Hold Time Min 3.5 3.5 1 1 Actual 6.86 6.86 1 1 Margin 3.36 3.36 0 0
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Figure 13 - Telecom DROP Bus Timing Diagram
0ns 1 LREFCLK, DCK tP DD tS TEL tP DD Telcom Drop Bus Data #1 tH TEL Data #2 tS TEL tH TEL Data #3 tP DD tS TEL tH TEL Data #4 tP DD tS TEL tH TEL Data #1 tP DD tS TEL 2 25ns 3 4 50ns 5
In reference to Figure 13, the sequence of events for one Telecom Drop bus clock cycle is as follows: 1. On the rising edge of LREFCLK, at the start of T1, the Telecom Drop bus is updated by the first valid data output of the SPECTRA-622, after the propagation delay tP DD. 2. On the rising edge of LREFCLK, at the start of T2, the TEMUX-84 samples the data from the Telecom Drop bus. All Telecom Drop signals require that the bus data be valid during setup time tS TEL and hold time tH TEL. The output propagation delays involved in Figure 13 are shown in the following table: Table 5
Name tP DD
Telecom Drop Bus Propagation Delays
Device SPECTRA-622 Description Propagation delay of LREFCLK to SPECTRA-622 Outputs going Valid Min 1 Max 6.5
The input constraints involved in Figure 13 are shown in the following table: Table 6
Name tS TEL tH TEL
Telecom Drop Bus Timing Constraints
Device TEMUX-84 TEMUX-84 Description Telecom Bus Set-up Time Telecom Bus Hold Time Min 3 0 Actual 6.36 1 Margin 3.36 1
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6.1.2 TEMUX-84 - SBS-Lite SBI336 Interface The SBI336 bus is a synchronous interface that carries data between the four TEMUX-84 devices and the SBS-Lite. The SBI336 bus is synchronized to a 77.76 MHz clock source. See Figure 14 below for a diagram of the SBI Add bus timing and Figure 15 for the Drop bus. Figure 14 - SBI ADD Bus Timing Diagram
0ns T1 SREFCLK tH SBIADD tS SBIADD tP CPLD SAC1FP tP SBIADD tH SBIADD tS SBIADD tP SBIADD SBI Add Bus tH AJUST tS AJUST tP AJUST AJUST_REQ tZ AJUST tP SBIADD tH SBIADD tS SBIADD tH SBIADD tS SBIADD tS SBIADD tP SBIADD tP CPLD T2 25ns T3 T4 50ns T5
TEMUX-84 #1
tH AJUST tS AJUST tP AJUST AJUST_REQ tZ AJUST
TEMUX-84 #2
tH AJUST tS AJUST tP AJUST AJUST_REQ tZ AJUST
TEMUX-84 #3
TEMUX-84 #4
tS AJUST tP AJUST AJUST_REQ
tZ AJUST
In reference to Figure 14, the sequence of events for one SBI Add bus clock cycle is as follows:
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1. On the rising edge of SREFCLK, at the start of T1, all signals on the SBI Add bus are updated by the SBS-Lite outputs after the propagation delay tP SBIADD. 2. Also, on the same edge of SREFCLK, the SAC1FP pulse is pulsed once every four frames or 4 x 9720 SREFCLKs, after a propagation delay of tP CPLD. 3. The AJUST_REQ signal is asserted by each TEMUX-84 to control the data rate of the Link Layer Device. The AJUST_REQ signal comes out of tristate after a delay of tP AJUST and returns to tristate on the next clock cycle, after a delay of tZ AJUST. 4. On the rising edge of SREFCLK, at the start of T2, the TEMUX-84 samples the data from the SBI Add bus and the SAC1FP input. All TEMUX-84 SBI inputs require that the data be valid during setup time tS SBIADD and hold time tH SBIADD. 5. Also, on the same edge of SREFCLK, the SBS-Lite samples the AJUST_REQ signal. The AJUST_REQ input requires a setup time of tS AJUST and a hold time tH AJUST. The output propagation delays involved in Figure 14 are shown in the following table: Table 7
Name tP SBIADD tP AJUST tZ AJUST tP CPLD
SBI Add Bus Propagation Delays
Device SBS TEMUX-84 TEMUX-84 CPLD Description Propagation delay of SREFCLK to SBS-Lite Outputs going Valid Propagation delay of SREFCLK to TEMUX-84 Output going Valid Propagation delay of SREFCLK to TEMUX-84 Output going to tristate Propagation delay of SREFCLK to TEMUX-84 Output going Valid Min 1 1 1 1 Max 7 6 5 7
The input constraints involved in Figure 14 are shown in the following table: Table 8
Name tS SBIADD tH SBIADD tS AJUST tH AJUST
SBI Add Bus Timing Constraints
Device TEMUX-84 TEMUX-84 SBS-Lite SBS-Lite Description TEMUX-84 input setup time TEMUX-84 input hold time SBS-Lite input setup time SBS-Lite input hold time Min 3 0 3 0 Actual 5.86 1 6.86 1 Margin 2.86 1 3.86 1
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Figure 15 - SBI DROP Bus Timing Diagram
0n s T1 SREFCLK tP C P L D tS S D C 1 F P tP C P L D S D C 1F P tH S D C 1FP T2 2 5n s T3 T4 5 0 ns T5
S D C 1F P
T E M U X -84 # 1
tZ S B ID R O P tH S B ID R O P tS S B ID R O P tP S B ID R O P S B I D ata tZ S BID R O P tH SB ID R O P tS S B ID R O P tP S B ID R O P S B I D a ta tZ S B ID R O P tH S B ID R O P tS SB ID R O P tP S B ID R O P
T E M U X -84 # 2
T E M U X -84 # 3
S BI D a ta tZ S B ID R O P tH S B ID R O P tS S B ID R O P tP SB ID R O P S B I D a ta
tZ S B ID R O P tH SB ID R O P T E M U X -84 # 4
In reference to Figure 15, the sequence of events for one SBI DROP bus clock cycle is as follows: 1. On the rising edge of SREFCLK, at the start of T1, The TEMUX-84 #1 puts valid data onto the SBI drop bus after the propagation delay tP SBIDROP. 2. On the rising edge of the T2 cycle, the SBS-Lite samples the data from the drop bus. The SBS-Lite requires a set-up time of tS SBIDROP and a hold time of tH SBIDROP to read the data. After the tZ SBIDROP delay, the TEMUX-84 #1 tristates its outputs, and TEMUX-84 #2 begins writing to the bus after a delay of tP SBIDROP. 3. The above steps are repeated for each of the four TEMUX-84s that can drive the data and control signals. When TEMUX #n is not driving the signals, its telecom ADD bus outputs are in a high impedance state.
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The output propagation delays involved in Figure 15 are shown in the following table: Table 9
Name tP CPLD tP SBIDROP tZ SBIDROP
SBI DROP Bus Propagation Delays
Device CPLD TEMUX-84 TEMUX-84 Description SREFCLK to data output delay SREFCLK to data valid delay SREFCLK to data tristate delay Min 1 1 1 Max 5 6 5
The input constraints involved in Figure 15 are shown in the following table: Table 10
Name tS SDC1FP tH SDC1FP tS SBIDROP tH SBIDROP
SBI DROP Bus Timing Constraints
Device TEMUX-84 TEMUX-84 SBS-Lite SBS-Lite Description Input set-up time Input hold time Input set-up time Input hold time Min 3 0 3 0 Actual 7.86 1 6.86 1 Margin 4.86 1 3.86 1
6.1.3 SPECTRA-622 - PCI9030 Interface The host processor can access the registers on the SPECTRA-622 via the PCI9030 Target Interface Device. The following diagrams show the timing that is required to read and write data between the SPECTRA-622 and PCI9030
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Figure 16 - SPECTRA-622 to PCI9030 Read Access Timing Diagram
0ns 1 Local Clk tP LOUT ADDR tP CPLD ADDR_A tP LOUT CS0 tP CPLD CS0 (CPLD) tP LOUT tS AR RD tP CPLD RD (CPLD) WR tP RD DATA_A Valid Data tS LIN tP CPLD DATA tP CPLD tH LIN Valid Data tZ RD tP CPLD tP LOUT tP CPLD Address Valid tP LOUT Address Valid tP CPLD tH AR tP LOUT 2 50ns 3 100ns 4 5 150ns 6 7 200ns 8
Address, Data, RD, WR and CS signals are further delayed by the CPLD (tP CPLD). In reference to Figure 16, the sequence of events for the PCI9030 to read data from the SPECTRA-622 is as follows. 1. On the rising edge of clock cycle 2, the PCI9030 outputs the required address and the appropriate chip select after a propagation delay of tP LOUT. 2. On the rising edge of clock cycle 3, the PCI9030 asserts the RD signal after a propagation delay of tP LOUT. The cycle in which the RD signal is asserted is set by the Read Strobe Delay bits in the LAS0BRD register of the PCI9030. For this interface, the value is 1. 3. After the propagation delay tP RD, the SPECTRA-622 puts valid data on the data bus. At the start of cycle 7, The PCI9030 reads the data from the data bus. The PCI 9030 inputs require a setup time of tS LIN and a hold time of tH
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LIN. Note that the PCI 9030 waits 6 cycles for the data to be placed on the data bus, the NRAD bits in LAS0BRD set this delay. 4. At the start of cycle 7, the PCI9030 de-asserts the address lines, RD and CS after a propogation delay of tP LOUT. The de-assertion of the RD signal causes the SPECTRA-622 data bus to tristate after a propagation delay tZ RD. The output propagation delays involved in Figure 16 are shown in the following table: Table 11
Name tP LOUT tP RD tZ RD tP CPLD
PCI9030 to SPECTRA-622 Read Propagation Delays
Device PCI9030 SPECTRA-622 SPECTRA-622 CPLD Description Local Clock edge to Local output delay RD to valid data delay RD negated to data tristate delay Propogation delay through CPLD Min 10 10.5 Max 70 20
The input constraints involved in Figure 16 are shown in the following table: Table 12
Name tS AR tH AR tS LIN tH LIN
PCI9030 to SPECTRA-622 Read Timing Constraints
Device SPECTRA-622 SPECTRA-622 PCI9030 PCI9030 Description Address to valid read setup Address to valid read hold Input setup time Input hold time Min 10 5 5 1 Actual 19.8 50.8 20.21 51 Margin 9.8 45.8 15.21 50
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Figure 17 - SPECTRA-622 to PCI9030 Write Access Timing
0ns 1 Local Clk tP LOUT ADDR tP CPLD ADDR_A tP LOUT CS0 tP CPLD CS0 (CPLD) RD tP LOUT WR tP CPLD tS AW WR (CPLD) tP LOUT DATA_A Valid Data tS DW tP CPLD DATA Valid Data tP CPLD tH DW tP LOUT tV WR tP CPLD tH AW tP LOUT tP CPLD Address Valid tP LOUT Address Valid tP CPLD tP LOUT 2 50ns 3 100ns 4 5 150ns 6 7
Address, Data, RD, WR and CS signals are further delayed by the CPLD (tP CPLD). In reference to Figure 17, the sequence of events for the PCI9030 to write data to the SPECTRA-622 is as follows: 1. On the rising edge of clock cycle 2, the PCI9030 outputs the required address and the appropriate chip select after a propagation delay of tP LOUT. 2. On the rising edge of clock cycle 3, the PCI9030 asserts the WR signal after a propagation delay of tP LOUT. The cycle in which the WR signal is asserted is set by the Write Strobe Delay bits in the LAS0BRD register of the PCI9030. For this interface, the value is 1. This delay is required to satisfy tS AW, the address to write setup time. 3. At the start of cycle 4, the PCI9030 puts valid data on the data bus after a propagation delay of tP LOUT.
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4. The SPECTRA-622 inputs require the data to be present for a setup time of tS DW and a hold time of tH DW. To satisfy these requirements, the PCI 9030 waits 2 cycles with valid data on the data bus. The NWDD bits in LAS0BRD set the wait delay. This wait delay also satisfies tV WR, the Valid Write Pulse width. 5. On the rising edge of clock cycle 5, the PCI9030 deasserts the WR signal after a propagation delay of tP LOUT. This causes the SPECTRA-622 to latch the data from the bus. The data must remain present on the bus for an additional tH DW. This is accomplished by setting the Write Cycle Hold bits in LAS0BRD to 1. The write cycle hold causes LDATA, CS, and ADDR to stay active until the rising edge of cycle 6, when they deassert after tP LOUT. The output propagation delays involved in Figure 17 are shown in the following table: Table 13
Name tP LOUT tP CPLD
PCI9030 to SPECTRA-622 Write Propagation Delays
Device PCI9030 CPLD Description Local Clock edge to Local output delay Delay through the CPLD Min 10 10.5 Max
The input constraints involved in Figure 17 are shown in the following table: Table 14
Name tS AW tV WR tH AW tS DW tH DW
PCI9030 to SPECTRA-622 Write Timing Constraints
Device SPECTRA-622 SPECTRA-622 SPECTRA-622 SPECTRA-622 SPECTRA-622 Description Address to valid write set-up Valid write pulse width Address to valid write hold Data to valid write set-up Data to valid write hold Min 10 40 5 20 5 Actual 30.3 60.61 30.8 30.3 30.3 Margin 20.3 20.61 25.3 10.3 25.3
6.1.4 TEMUX-84 - PCI9030 Interface The host processor can access the registers on the each of the four TEMUX-84 devices via the PCI9030 Target Interface Device. There will be one chip select and address range in the PCI9030 allocated for all TEMUX-84 devices. The CPLD on the card will use this chip select signal plus the information on the address bus to allow individual access to each of the TEMUX-84 devices. See Section 8.1 below for a detailed description of the CPLD address decoding implementation. The read and write accesses of the TEMUX-84's are shown below in Figure 18 and Figure 19 - PCI9030 to TEMUX-84 Write Access Timing
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Diagram respectively. Please refer to the respective device datasheets for the timing data. Figure 18 - TEMUX-84 to PCI9030 Read Access Timing Diagram
0ns 1 Local Clk tP LOUT ADDR tP CPLD ADDR_B tP LOUT CS1 tP CPLD CS1 (CPLD) tP CPLD T M X_CS[3:0] tP LOUT tS AR RD tP CPLD RD (CPLD) WR tP RD DAT A_B Valid Data tP CPLD tS LIN tH LIN Valid Data tP CP tZ RD tP CPLD tP LOUT tP CPLD tP CPLD tP LOUT Address Valid tP CPLD tH AR tP LOUT 2 50ns 3 100ns 4 5 150ns 6 7
DAT A
Address, Data, RD, WR and CS signals are further delayed by the CPLD (tP CPLD). In reference to Figure 18, the sequence of events for the PCI9030 to read data from any TEMUX-84 is as follows: 1. On the rising edge of clock cycle 2, the PCI9030 outputs the required address after a propagation delay of tP LOUT. An appropriate chip select is outputted by the PCI9030 and then the individual TEMUX-84 chip select is decoded after a delay of tP LOUT. 2. On the rising edge of clock cycle 3, the PCI9030 asserts the RD signal after a propagation delay of tP LOUT. The cycle in which the RD signal is asserted is
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set by the Read Strobe Delay bits in the LAS1BRD register of the PCI9030. For this interface, the value is 1. 3. After the propagation delay tP RD, the TEMUX-84 puts data on the data bus. At the start of cycle 5, The PCI9030 reads the data from the data bus. The PCI 9030 inputs require a setup time of tS LIN and a hold time of tH LIN. Note that the PCI 9030 waits 2 cycle for the data to be placed on the data bus, this delay is set by the NRAD bits in LAS1BRD. 4. Also at the start of cycle 5, the PCI9030 de-asserts the RD, CS, and address lines after the propagation delay, tP LOUT. The de-assertion of the RD signal causes the TEMUX-84 data bus to tristate after a propagation delay tZ RD. The output propagation delays involved in Figure 18 are shown in the following table: Table 15
Name tP LOUT tP RD tZ RD tP CPLD
PCI9030 to TEMUX-84 Read Propagation Delays
Device PCI9030 TEMUX-84 TEMUX-84 CPLD Description Local Clock edge to Local output delay RD to valid data delay RD negated to data tristate delay CS Decode Input to Output Delay Min 10 10.5 Max 30 20 -
The input constraints involved in Figure 18 are shown in the following table: Table 16
Name tS AR tH AR tS LIN tH LIN
PCI9030 to TEMUX-84 Read Timing Constraints
Device TEMUX-84 TEMUX-84 PCI9030 PCI9030 Description Address to valid read setup Address to valid read hold Input setup time Input hold time Min 10 5 5 1 Actual 19.8 20.5 29.91 20.7 Margin 9.8 15.5 24.91 19.7
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Figure 19 - PCI9030 to TEMUX-84 Write Access Timing Diagram
0ns 1 Local Clk tP LOUT ADDR tP CPLD ADDR_B tP LOUT CS1 tP CPLD CS1 (CPLD) tP CPLD T MX_CS[3:0] RD tP LOUT WR tP CPLD tS AW WR (CPLD) tP LOUT DAT A_B tP CPLD DAT A Valid Data Valid Data tS DW tH DW tP CPLD tP LOUT tV WR tP CPLD tH AW tP LOUT tP CPLD tP CPLD Address Valid tP LOUT Address Valid tP CPLD tP LOUT 2 50ns 3 100ns 4 5 150ns 6
Address, Data, RD, WR and CS signals are further delayed by the CPLD (tP CPLD). In reference to Figure 19, the sequence of events for the PCI9030 to write data to the TEMUX-84 is as follows: 1. On the rising edge of clock cycle 2, the PCI9030 outputs the required address and the appropriate chip select after a propagation delay of tP LOUT. 2. On the rising edge of clock cycle 3, the PCI9030 puts valid data on the data bus and asserts the WR signal after a propagation delay of tP LOUT. The cycle in which the WR signal is asserted is set by the Write Strobe Delay bits in the LAS1BRD register of the PCI9030. For this interface, the value is 1. This delay is required to satisfy tS AW, the address to write setup time. 3. The TEMUX-84 inputs require the data to be present for a setup time of tS DW. To satisfy these requirements, the PCI 9030 waits 1 cycles with valid
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data on the data bus. The NWDD bits in LAS1BRD set the wait delay. This wait delay also satisfies tV WR, the Valid Write Pulse width. 4. On the rising edge of clock cycle 5, the PCI9030 deasserts the WR signal after a propagation delay of tP LOUT. This causes the TEMUX-84 to latch the data from the bus. The data must remain present on the bus for an additional tH DW. This is accomplished by setting the Write Cycle Hold bits in LAS1BRD to 1. The write cycle hold causes LDATA, CS, and ADDR to stay active until the rising edge of cycle 6, when they are de-asserted after tP LOUT. The output propagation delays involved in Figure 19 are shown in the following table: Table 17
Name tP LOUT tP CPLD
PCI9030 to TEMUX-84 Write Propagation Delays
Device PCI9030 CPLD Description Local Clock edge to Local output delay CS Decode Input to Output Delay Min 10 10.5 Max -
The input constraints involved in Figure 19 are shown in the following table: Table 18
Name tS AW tV WR tH AW tS DW tH DW
PCI9030 to TEMUX-84 Write Timing Constraints
Device TEMUX-84 TEMUX-84 TEMUX-84 TEMUX-84 TEMUX-84 Description Address to valid write set-up Valid write pulse width Address to valid write hold Data to valid write set-up Data to valid write hold Min 10 40 5 20 5 Actual 24.8 55.11 26.8 55.11 26.8 Margin 14.8 15.11 19.8 35.11 19.8
6.1.5 SBS-Lite - PCI9030 Interface The host processor can access the registers on the SBS-Lite via the PCI9030 Target Interface Device. There will be one chip select and address range in the PCI9030 allocated for the SBS-lite. An explanation of timing, delays, and constraints will not be shown in this section since all timing information is identical between the SBS-Lite and the TEMUX-84. Please refer to Section 6.1.4 for all of the necessary information.
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6.1.6 XC95288XL CPLD - PCI9030 Interface The host processor can access the internal registers of the XC95288XL CPLD via the PCI9030 Target Interface Device. There will be one chip select and address range in the PCI9030 allocated for the CPLD. See Section 8.1 belowbelow for a detailed description of the CPLD address decoding implementation. The read and write accesses to the CPLD are shown below in Figure 20 and Figure 21 - PCI9030 to CPLD Write Access Timing Diagram respectively. Please refer to the respective device datasheets for complete timing data. Figure 20 - PCI9030 to CPLD Read Access Timing Diagram
0ns 1 Local Clk tP LOUT ADDR tP LOUT CS3 tP CPLD CS3 decode tP LOUT RD WR tS LIN tP CPLD1 Valid Data tP CPLD1 tH LIN tP LOUT tP CPLD Address Valid tP LOUT tP LOUT 2 50ns 3 100ns 4 5 150ns 6
DATA
Address, Data, RD, WR and CS signals are further delayed by the CPLD (tP CPLD). In reference to Figure 20, the sequence of events for the PCI9030 to read data from the CPLD is as follows: 1. On the rising edge of clock cycle 2, the PCI9030 outputs the required address and the appropriate chip select after a propagation delay of tP LOUT. 2. On the rising edge of clock cycle 3, the PCI9030 asserts the RD signal after a propagation delay of tP LOUT. The cycle in which the RD signal is asserted is
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set by the Read Strobe Delay bits in the LAS3BRD register of the PCI9030. For this interface, the value is 1. 3. After the propagation delay tP CPLD1, the XC95288 puts valid data on the data bus. At the start of cycle 5, the PCI9030 reads the data from the data bus. The PCI 9030 inputs require a setup time of tS LIN and a hold time of tH LIN. Note the PCI 9030 waits 1 cycle for the data to be placed on the data bus, this delay is set by the NRAD bits in LAS1BRD 4. Also at the start of cycle 5, the PCI9030 de-asserts the RD, CS, and address lines after the propagation delay, tP LOUT. The de-assertion of the RD signal causes the CPLD data bus pins to tristate after a propagation delay tP CPLD1. The output propagation delays involved in Figure 20 are shown in the following table: Table 19
Name TP LOUT TP CPLD
PCI9030 to XC95288 Read Propagation Delays
Device PCI9030 CPLD Description Local Clock edge to Local output delay Propogation delay Min 10 10.5 Max
The input constraints involved in Figure 20 are shown in the following table: Table 20
Name TS LIN TH LIN
PCI9030 to XC95288 Read Timing Constraints
Device PCI9030 PCI9030 Description Input setup time Input hold time Min 5 1 Actual 35.61 25 Margin 30.61 24
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Figure 21 - PCI9030 to CPLD Write Access Timing Diagram
0ns 1 LCLK tP LOUT ADDR tP LOUT CS3 tP CPLD CS3 (CPLD) RD tP LOUT WR tS CPLD tH CPLD tP LOUT Valid Data tP LOUT tP LOUT tP CPLD Address Valid tP LOUT tP LOUT 25ns 2 50ns 75ns 3 100ns 4
DATA
Address, Data, RD, WR and CS signals are further delayed by the CPLD (tP CPLD). In reference to Figure 21, the sequence of events for the PCI9030 to write data to the XC95288 CPLD is as follows: 1. On the rising edge of clock cycle 2, the PCI9030 outputs the required address and the appropriate chip select after a propagation delay of tP LOUT. 2. On the rising edge of clock cycle 4, the PCI9030 puts valid data on the data bus and asserts the WR signal after a propagation delay of tP LOUT. The cycle in which the WR signal is asserted is set by the Write Strobe Delay bits in the LAS3BRD register of the PCI9030. For this interface, the value is 2. 3. The CPLD inputs require the data to be present for a setup time of tS CPLD. A wait cycle is required in order to meet the constraints. The NWDD bits in LAS3BRD set the wait delay, and its set to 1. 4. The CPLD latches the data on the rising edge of clock cycle 6 and then the PCI9030 deasserts the DATA, ADDR, CS3, and WR signals after a propagation delay of tP LOUT. The data must remain present on the bus for an additional tH CPLD. This requirement is satisfied since the hold time is
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less than the propagation delay of the outputs. For longer hold times, the Write Cycle Hold bits in LAS3BRD could be used. The output propagation delays involved in Figure 21 are shown in the following table: Table 21
Name tP LOUT tP CPLD
PCI9030 to XC95288 CPLD Write Propagation Delays
Device PCI9030 XC95288XL Description Local Clock edge to Local output delay CPLD propagation delay Min 10 10.5 Max
The input constraints involved in Figure 21 are shown in the following table: Table 22
Name tS CPLD tH CPLD
PCI9030 to XC95288 CPLD Write Timing Constraints
Device XC95288 CPLD XC95288 CPLD Description Input Setup time Input Hold time Min 3.7 0 Actual 10.3 20 Margin 6.6 20
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6.2
Power Estimate and Thermal Analysis Table 23 1.8V SBS-Lite TEMUX-84 TOTAL Power Consumption by Supply Rail for Each Device Quantity 1 4 Power (Watts) 0.454 3.88 4.334 Current (mA) 252 2000 2252
3.3V SBS-Lite TEMUX-84 SPECTRA-622 PCI 9030 PI49FCT3805 OSC EP26 XC95288XL HP HFCT-5208 PECl OSC TOTAL
Quantity 1 4 1 1 5 5 1 1 1
Power (Watts) 0.95 0.898 3.102 0.495 1.32 0.924 0.561 0.792 0.198 9.979
Current (mA) 288 272 940 150 400 280 170 240 60 3024
Once accurate data for the TEMUX-84 and SBS-Lite is available, calculations should be done to show the total draw current draw through the 1.8V and 3.3V regulators, which will then reflect the total current drawn from the 5V and 3.3V cPCI power rails.
The Power data calculated using I = current (A) IDDOP P = power (Watt) V = voltage (Volts) e.g. VDDQ
I=P/V where
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6.2.1 Titania Power Modules The Austin Power Module Series delivers high quality, ultra compact, DC-DC conversion. The OC12 Line Card requires two power modules. The TPM_108612961 performs 5V to 3.3V conversion and the TPM_108612920 performs 3.3V to 1.8V conversion. Both modules are rated to operate in an ambient temperature range of 0C to 80C. The datasheets provide thermal derating curves, which provide max output current at specified temperatures. The TPM_108612961 is supplying approximately 3024 mA to the board. In accordance with the derating curve for the case of zero air flow, the power module can provide the required current up to an ambient temperature of 47C. The TPM_108612920 is supplying approximately 2252 mA to the board In accordance with the derating curve for the case of zero air flow, the power module can provide the required current up to an ambient temperature of 70C.
6.3
Signal Integrity Simulations The following sections contain pre-layout simulations for the Telecom Bus, SBI336 Bus, and the PCI9030 Microprocessor Interface Bus. Since these simulations were performed before layout, certain trace lengths may change to accommodate physical restrictions. It is recommended that the approximate lengths, termination values, and bus topology not change without using a simulation program to verify that signal integrity is maintained. In each of the simulation layout diagrams, each driver and receiver represents the internal logic of each device pin. Microstrip represents the trace length from the device pin to via. Stripline is representative of the internal layer trace from one pin via to another. The stripline length and connection topology is very important to the success of these simulations. Other topologies should be simulated before being considered for routing.
6.3.1 Telecom Bus The layout for the Telecom bus is shown below in Figure 22.
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Figure 22 - Telecom ADD Bus Simulation
U(A0) PM5313_SPECTRA_... ad[0] CELL:A0 0.0 ohms RS(A0) 65.0 ohms 18.188 ps 0.125 in Microstrip CELL:B0 65.8 ohms 527.070 ps 3.000 in Stripline CELL:C0 22.0 ohms RS(C0) U(D0) PM8316_TEMUX_84 ladata_0 65.0 ohms 18.188 ps 0.125 in Microstrip CELL:D0
U(D1) PM8316_TEMUX_84 ladata_0 CELL:B1 65.8 ohms 527.070 ps 3.000 in Stripline CELL:C1 22.0 ohms RS(C1) 65.0 ohms 18.188 ps 0.125 in Microstrip CELL:D1
U(D2) PM8316_TEMUX_84 ladata_0 CELL:B2 65.8 ohms 175.690 ps 1.000 in Stripline CELL:C2 22.0 ohms RS(C2) 65.0 ohms 18.188 ps 0.125 in Microstrip CELL:D2
U(D3) PM8316_TEMUX_84 ladata_0 CELL:B3 65.8 ohms 527.070 ps 3.000 in Stripline CELL:C3 22.0 ohms RS(C3) 65.0 ohms 18.188 ps 0.125 in Microstrip CELL:D3
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Figure 23 - Telecom DROP Bus Simulation
VpullUp=3.300 V U(A0) PM5313_SPECTRA_... dd[0] CELL:A0 0.0 ohms RS(A0) 65.0 ohms 29.100 ps 0.200 in Microstrip CELL:B0 10.0 K ohms RP(B0) 65.8 ohms 527.070 ps 3.000 in Stripline CELL:C0 0.0 ohms RS(C0) U(D0) PM8316_TEMUX_84 lddata_0 65.0 ohms 29.100 ps 0.200 in Microstrip CELL:D0
U(D1) PM8316_TEMUX_84 lddata_0 CELL:A1 10.0 M ohms RD(A1) 65.8 ohms 175.690 ps 1.000 in Stripline CELL:B1 65.8 ohms 527.070 ps 3.000 in Stripline CELL:C1 0.0 ohms RS(C1) 65.0 ohms 29.100 ps 0.200 in Microstrip CELL:D1
VpullDn=0.000 V U(D2) PM8316_TEMUX_84 lddata_0 CELL:B2 65.8 ohms 527.070 ps 3.000 in Stripline CELL:C2 0.0 ohms RS(C2) 65.0 ohms 29.100 ps 0.200 in Microstrip CELL:D2
U(D3) PM8316_TEMUX_84 lddata_0 CELL:B3 65.8 ohms 527.070 ps 3.000 in Stripline CELL:C3 0.0 ohms RS(C3) 65.0 ohms 29.100 ps 0.200 in Microstrip CELL:D3
U(A4) PI49FCT3805Q OA0 CELL:A4 65.0 ohms 29.100 ps 0.200 in Microstrip CELL:B4 47.0 ohms RS(B4) 65.8 ohms 702.760 ps 4.000 in Stripline CELL:C4
U(D4) PM8316_TEMUX_84 lrefclk 65.0 ohms 29.100 ps 0.200 in Microstrip CELL:D4
The pull down on the drop bus is added in order to simulate effects of the mictor connector. The 77.76 MHz clock drives the telecom bus. The simulated waveform is shown below in Figure 24.
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Figure 24 - Telecom Bus Clock Signal
77.76 MHz Telecom Bus Clock 7.000 volts Probe 1:U(A4) Probe 2:U(D4)
1 V/div 0.0 volts -2.000 volts 0.000ns
5 nsec/div
50.000ns
The data on the Telecom Bus is sampled on every rising clock edge. Since the clock frequency is 77.76 MHz, the data rate is half the clock frequency, 38.89 MHz. A simulation of a TEMUX-84 writing data to the SPECTRA-622 is shown in Figure 25 below. Figure 25 - Telecom ADD Bus Data Signals
Comment: Telecom TEMUX-84 to SPECTRA-622 Data Signal 7.000 volts Probe Probe
1 V/div
0.0 volts -2.000 volts 0.000ns
5 nsec/div
50.000ns
The data transmission on the bus is simulated in both the ADD and DROP directions, since the drivers and receivers of each device have slightly different characteristics. Figure 26 shows the SPECTRA-622 driving the Telecom bus.
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Figure 26 - Telecom DROP Bus Data Signals
7.000 volts Comment: Telecom Drop Probe 1:U(A0) Probe Probe Probe
1 V/div
0.0 volts -2.000 volts 0.000ns
5 nsec/div
50.000ns
For some sections of the Telecom bus, a termination resistor is placed near the signal driver. Values of the resistors are chosen to lower excessive overshoot/undershoot. 6.3.2 SBI336 Bus The layout for the SBI336 bus is shown in Figure 27. It is important to include the entire bus in this simulation, since each tri-stated output on the bus affects the signal integrity.
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Figure 27 - SBI336 DROP Bus Simulation
U(A0) PM8316_TEMUX_84 sddata_0_mvid_4 CELL:A0 22.0 ohms RS(A0) 65.0 ohms 29.100 ps 0.200 in Microstrip CELL:B0 65.8 ohms 281.104 ps 1.600 in Stripline
U(A1) PM8316_TEMUX_84 sddata_0_mvid_4 CELL:A1 22.0 ohms RS(A1) 65.0 ohms 29.100 ps 0.200 in Microstrip CELL:B1 65.8 ohms 210.828 ps 1.200 in Stripline CELL:C1 65.8 ohms 351.380 ps 2.000 in Stripline CELL:D1 0.0 ohms RS(D1)
U(E1) PM8610_SBS ID[1][0] 65.0 ohms 29.530 ps 0.200 in Microstrip CELL:E1
U(A2) PM8316_TEMUX_84 sddata_0_mvid_4 CELL:A2 22.0 ohms RS(A2) 65.0 ohms 29.100 ps 0.200 in Microstrip CELL:B2 65.8 ohms 210.828 ps 1.200 in Stripline
U(A3) PM8316_TEMUX_84 sddata_0_mvid_4 CELL:A3 22.0 ohms RS(A3) 65.0 ohms 29.100 ps 0.200 in Microstrip CELL:B3 65.8 ohms 281.104 ps 1.600 in Stripline
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Figure 28 - SBI336 ADD Bus Simulation
U(A0) PM8316_TEMUX_84 sadata_0_mved_5 CELL:A0 65.0 ohms 29.100 ps 0.200 in Microstrip CELL:B0 0.0 ohms RS(B0) 65.8 ohms 439.225 ps 2.500 in Stripline
U(A1) PM8316_TEMUX_84 sadata_0_mved_5 CELL:A1 65.0 ohms 29.100 ps 0.200 in Microstrip CELL:B1 0.0 ohms RS(B1) 65.8 ohms 439.225 ps 2.500 in Stripline
U(A2) PM8316_TEMUX_84 sadata_0_mved_5 CELL:A2 65.0 ohms 29.100 ps 0.200 in Microstrip CELL:B2 0.0 ohms RS(B2) 65.8 ohms 439.225 ps 2.500 in Stripline CELL:C2 65.8 ohms 175.690 ps 1.000 in Stripline CELL:D2 22.0 ohms RS(D2)
U(E2) PM8610_SBS OD[1][0] 65.0 ohms 29.100 ps 0.200 in Microstrip CELL:E2
U(A3) PM8316_TEMUX_84 sadata_0_mved_5 CELL:A3 65.0 ohms 29.100 ps 0.200 in Microstrip CELL:B3 0.0 ohms RS(B3) 65.8 ohms 439.225 ps 2.500 in Stripline
U(A4) PI49FCT3805Q OA0 CELL:A4 65.0 ohms 29.100 ps 0.200 in Microstrip CELL:B4 47.0 ohms RS(B4) 65.8 ohms 439.225 ps 5.000 in Stripline CELL:C4
U(D4) PM8610_SBS SREFCLK 65.0 ohms 29.100 ps 0.200 in Microstrip CELL:D4
The 77.76 MHz clock drives the SBI bus. The simulated waveform is shown below in Figure 29.
Figure 29 - SBI336 Clock Signal
7.000 volts Comment: SBI336 Drop Bus Signal Probe 4:U(A4) Probe 5:U(D4)
1 V/div 0.0 volts -2.000 volts 0.000ns
2 nsec/div
20.000ns
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The data on the SBI336 Bus is sampled on every rising clock edge. Since the clock frequency is 77.76 MHz, the data rate is half the clock frequency, 38.89 MHz. A simulation of a TEMUX-84 writing data to the SBS-Lite is shown in Figure 30 below. Figure 30 - SBI336 DROP Bus Waveform
7.000 volts Comment: SBI336 Drop Bus Probe 1:U(A1) Probe 2:U(E1)
1 V/div 0.0 volts -2.000 volts 0.000ns
5 nsec/div
50.000ns
The data transmission on the bus is simulated in both the ADD and DROP directions, since the drivers and receivers of each device have slightly different characteristics. Figure 31 shows the SBI336 ADD bus. Figure 31 - SBI336 ADD Bus Waveform
7.000 volts Comment: SBI336 Add Bus Signal Probe 1:U(E2) Probe 2:U(A1)
1 V/div 0.0 volts -2.000 volts 0.000ns
5 nsec/div
50.000ns
For the clock lines of the SBI336 bus, the desired series termination value will be 47, to be placed near the signal driver.
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For the data lines that are shared between all bus devices, the simulations have shown that using a series termination resistor near each device on a multi-driver bus reduces the reflections from the driving device. Therefore, each device will have a series termination located near the pin. The optimum value has been found to be 22. Values lower than those tend to cause excessive overshoot/undershoot, while larger values will eventually reduce the current that the driver can supply. 6.3.3 Microprocessor Interface 6.3.3.1 Data Bus The OC12 Line card has the option of choosing from two possible microprocessors. Using a specified jumper, one can choose either of the two microprocessors. For the following simulation, the PCI9030 controller is used. The address and data signals are routed via the CPLD. The microprocessor interface connects between 8 different devices, with the PCI9030 performing read and write operations on the other 7 devices, the initial simulations indicated that the PCI9030 cannot drive that many devices at the required bus speed. See Section 4.7.1 for a diagram of the microprocessor interface topology. The data lines between the XC95288XL and devices require series termination since both are strong drivers and cause excessive overshoot/undershoot when not terminated. Refer to Figure 32 for the PCI9030 to CPLD simulation layout. Figure 32 - PCI9030 / XC95288XL Simulation Layout
U (A P C I9 0 5 0 _ P 0) QFP LAD 0 U (D X C 9 5 2 8 8 X 0 )_ T L Q 208 io b 6 7 .4 C E L L : 0 .0 2h .0 4 2 9 h C0 0 .2 0 0 R S (C 0) i M ic r o s ti
C E L L : 2 2 .0 h A0 R S (A 0)
6 7 .4 2h . 0 4 2 9 0 .2 0 0 i M ic r o s ti
CELL: B0
6 5 .8 8 7 8 .4 5 0 h 5 .0 0 0 i S trip li
CELL: D0
U (A P C I9 0 5 0 _ P 1) LA1 QFP 0
C E L L : 2 2 .0 h A1 R S (A 1)
6 7 .4 2h . 0 4 2 9 0 .2 0 0 i M ic r o s ti
CELL: B1
6 5 .8 8 7 8 .4 5 0 h 5 .0 0 0 i S trip li
CELL: C1
U (D X C 9 5 2 8 8 X 1 )_ T L io Q 208 b 6 7 .4 2h .0 4 2 9 0 .2 0 0 i M ic r o s ti
CELL: D1
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Figure 33 - PCI9030 / XC95288XL Data Waveforms
7.000 volts
Comment: Write Data (PCI9030 to XC95288XL) Probe 1:U(A0) Probe 2:U(D0)
1 V/div 0.0 volts 2.000 volts 0.000ns
10 nsec/div
100.000ns
7.000 volts
Comment: Read Data (PCI9030 to XC95288XL) Probe 1:U(A0) Probe 2:U(D0)
1 V/div 0.0 volts -2.000 volts 0.000ns
10 nsec/div
100.000ns
Figure 34 - PCI9030 / XC95288XL Address Waveforms
7.000 volts Comment: Address Bus (PCI9030 to XC95288XL) Probe 1:U(A1) Probe 2:U(D1)
1 V/div 0.0 volts -2.000 volts 0.000ns
10 nsec/div
100.000ns
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The microprocessor bus consists of two separate sections. Section 1 refers to the four TEMUX-84s device group and the other two devices group is labelled section 2. (The TEMUX-84 devices are all grouped on the same bus to simplify the bus design.) Since only one transceiver can be active during a read operation, the TEMUX-84 chip select pin is used to select which transceiver is currently active. Figure 35 - Microprocessor Interface Data Bus Simulation Layout Section 1
U(A0) XC95288XL_TQ208... iob CELL:A0 22.0 ohms RS(A0) 67.4 ohms 29.042 ps 0.200 in Microstrip CELL:B0 65.8 ohms 351.380 ps 2.000 in Stripline CELL:C0 65.8 ohms 614.915 ps 3.500 in Stripline CELL:D0 22.0 ohms RS(D0) U(E0) PM8316_TEMUX_84 d_0 67.4 ohms 29.042 ps 0.200 in Microstrip CELL:E0
U(E1) PM8316_TEMUX_84 d_0 CELL:C1 65.8 ohms 395.303 ps 2.250 in Stripline CELL:D1 22.0 ohms RS(D1) 67.4 ohms 29.042 ps 0.200 in Microstrip CELL:E1
U(E2) PM8316_TEMUX_84 d_0 CELL:C2 65.8 ohms 351.380 ps 2.000 in Stripline CELL:D2 22.0 ohms RS(D2) 67.4 ohms 29.042 ps 0.200 in Microstrip CELL:E2
U(E3) PM8316_TEMUX_84 d_0 CELL:C3 65.8 ohms 527.070 ps 3.000 in Stripline CELL:D3 22.0 ohms RS(D3) 67.4 ohms 29.042 ps 0.200 in Microstrip CELL:E3
Section 2
U(A4) XC95288XL_TQ208... iob CELL:A4 0.0 ohms RS(A4) 67.4 ohms 29.042 ps 0.200 in Microstrip CELL:B4 65.8 ohms 351.380 ps 2.000 in Stripline CELL:C4 65.8 ohms 395.303 ps 2.250 in Stripline CELL:D4 U(E4) PM5313_SPECTRA_... d[0] 22.0 ohms RS(D4) 67.4 ohms 29.042 ps 0.200 in Microstrip CELL:E4
U(E5) PM8610_SBS D[0] CELL:C5 65.8 ohms 527.070 ps 3.000 in Stripline CELL:D5 22.0 ohms RS(D5) 67.4 ohms 29.042 ps 0.200 in Microstrip CELL:E5
There is no clock simulation required for the microprocessor interface, since the clock is only used by the PCI9030 to synchronously read in data. All writes to the other devices are asynchronously controlled by the PCI9030. Since the clock frequency of the local bus is 33.33 MHz, the data rate is half the clock frequency, 16.67 MHz.
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Please refer to Figure 36 and Figure 37 below, which show the waveforms for read and write operations on both sections of the microprocessor data bus interface. Figure 36 - Microprocessor Data Bus, Section 1 Waveforms
7.000 volts Comment: Microprocessor Interface (section 1) Write Comment: Microprocessor Interface (section 1) Read 7.000 volts Probe 1:U(A0) Probe 1:U(A0) Probe 2:U(E0) Probe 2:U(E0) Probe 3:U(E1) Probe 4:U(E2) 1 V/div 0.0 volts -2.000 volts 0.000ns
1 V/div 0.0 volts -2.000 volts 0.000ns
10 nsec/div
100.000ns
10 nsec/div
100.000ns
Figure 37 - Microprocessor Data Bus, Section 2 Waveforms
7.000 volts Comment: Microprocessor Interface (section 2) Write Comment: Microprocessor Interface (section 2) read 7.000 volts Probe 1:U(A4) Probe 1:U(A4) Probe 2:U(E4) Probe 2:U(E4) Probe 3:U(E5)
1 V/div 0.0 volts -2.000 volts 0.000ns
1 V/div 0.0 volts -2.000 volts 0.000ns
10 nsec/div
100.000ns
10 nsec/div
100.000ns
For some of the multi-point, bi-directional data lines, the simulations have shown that a series termination resistor is required near each device to reduces the reflections from the driving device. Therefore, those devices will have a series termination. The optimum value has been found to be 22. Values lower than those tend to cause excessive overshoot/undershoot, while larger values will eventually reduce the current that the driver can supply. 6.3.3.2 Address Bus The address bus is designed using a similar methodology to the data bus, with the exception being that the bus is uni-directional. The address bus is still divided into two sections generated by the CPLD, then connected as shown below in Figure 38. Section 1 as before controls the four TEMUX-84s and section 2 controls the other three devices.
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Figure 38 - Microprocessor Interface Address Bus Simulation Layout Section 1
U(A0) XC95288XL_TQ208... iob CELL:A0 22.0 ohms RS(A0) 67.4 ohms 29.042 ps 0.200 in Microstrip CELL:B0 65.8 ohms 351.380 ps 2.000 in Stripline CELL:C0 65.8 ohms 614.915 ps 3.500 in Stripline CELL:D0 U(E0) PM8316_TEMUX_84 a_0 67.4 ohms 29.042 ps 0.200 in Microstrip CELL:E0
U(E1) PM8316_TEMUX_84 a_0 CELL:C1 65.8 ohms 395.303 ps 2.250 in Stripline CELL:D1 67.4 ohms 29.042 ps 0.200 in Microstrip CELL:E1
U(E2) PM8316_TEMUX_84 a_0 CELL:C2 65.8 ohms 351.380 ps 2.000 in Stripline CELL:D2 67.4 ohms 29.042 ps 0.200 in Microstrip CELL:E2
U(E3) PM8316_TEMUX_84 a_0 CELL:C3 65.8 ohms 527.070 ps 3.000 in Stripline CELL:D3 67.4 ohms 29.042 ps 0.200 in Microstrip CELL:E3
Section 2
U(A4) XC95288XL_TQ208... iob CELL:A4 22.0 ohms RS(A4) 67.4 ohms 29.042 ps 0.200 in Microstrip CELL:B4 65.8 ohms 351.380 ps 2.000 in Stripline CELL:C4 65.8 ohms 395.303 ps 2.250 in Stripline CELL:D4 U(E4) PM5313_SPECTRA_... a[0] 67.4 ohms 29.042 ps 0.200 in Microstrip CELL:E4
U(E5) PM8610_SBS A[0] CELL:C5 65.8 ohms 527.070 ps 3.000 in Stripline CELL:D5 67.4 ohms 29.042 ps 0.200 in Microstrip CELL:E5
The address lines change at the same frequency as the data lines, 16.67 MHz. Please refer to Figure 39 below, which show the waveforms for both sections of the microprocessor address bus interface.
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Figure 39 - Microprocessor Address Bus Waveforms
Comment: Microprocessor Address Interface (section 1) 7.000 volts Probe 1:U(A0) Probe 2:U(E0) Probe 3:U(E1) Comment: Microprocessor Address Interface (section 2) 7.000 volts Probe 1:U(A4) Probe 2:U(E4) Probe 3:U(E5)
1 V/div 0.0 volts -2.000 volts 0.000ns
1 V/div 0.0 volts -2.000 volts 0.000ns
10 nsec/div
100.000ns
10 nsec/div
Section 1 Address
Section 2 Address
100.000ns
For the multi-point, uni-directional address lines, the simulations have shown that using a series termination resistor near the driver reduces the overshoot and undershoot of the signal. Therefore, only the driving device will have a series termination that should be physically located near the output. The optimum value has been found to be 22.
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7 7.1
DESIGN DETAILS Component Placement The overall placement strategies of the components are: Place the analog circuitry away from the digital circuitry. Keep the analog transmit side components separate from the analog receive side components. For high-speed data lines on bi-directional busses, series termination resistors are placed near each pin on the bus to reduce reflections. For high-speed data lines on uni-directional busses, source termination resistors are placed near the driver outputs to reduce ringing. Ringing usually occurs when the driver is driving a smaller number of gates. The Telecom bus and the SBI bus should be routed so that the bus length is approximately the same to each TEMUX-84 from the SPECTRA-622 or the SBSLite. The PCI Bridge and the CPLD should be placed so that the I/O interface bus can be routed perpendicular to the telecom/SBI buses. This is not a critical requirement, but it helps make routing more efficient and reduces crosstalk. All pull up/down resistors are placed near the output pins. The oscillator is placed in a quiet digital section as noise on its power supply will cause jitter on the output, and the oscillator itself generates noise that may affect sensitive analog circuits. The PCI Bridge device is placed such that all the PCI interface traces are within the specified length limits of the PCI Rev. 2.1 Specification. All decoupling capacitors are placed near the power supply pins. The power supply should be placed in a low-component density area of the board so that sufficient copper on the component layer can be used for heatsinking of the supply regulators. (See Section 6.2 for the calculations of required copper surface area) Use a single plane for both analog and digital grounds.
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The approximate placement of major components is shown in Figure 40 below. (The diagram is drawn to scale.) Figure 40 - Card Floorplan
LEDs
Serial Port Ethernet Jack 1 cm 1 inch
OPTICS TEMUX-84
Processor Board TEMUX-84 SPECTRA-622 SBS-Lite
TEMUX-84
Oscillators
XC95288 CPLD TEMUX-84
PCI9030 Power Supply CPCI
LVDS Connector
7.2
Layer Stacking and Impedance Control The OC-12 Line Card has 12 layers. Six layers are signal layers and six layers are power/ground layers. It important to orient the layers in the stacking arrangement shown in Figure 41 in order to minimize EMI and crosstalk from the signal layers.
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Figure 41 - Layer Stack
SIG1 GND 5V SIG2 SIG3 3V3 GND SIG4 SIG5 1V8 GND SIG6
To reduce signal degradation due to reflection and radiation, the traces that carry high speed signals should be treated as micro strip transmission lines with controlled impedance and matched resistive termination. Given characteristic impedance Zo, the dielectric thickness is proportional to trace width. A small dielectric thickness will result in the traces being too thin to be accurately fabricated. Wider traces can be more precisely manufactured, but they take up too much board space. Therefore, the thickness of the board for a given trace impedance and adequate trace width should be chosen so that the traces take up as little board space as possible yet still leaving enough margin to allow accurate fabrication. The dielectric material and thickness of the board is chosen such that when using a 6-mil trace, the characteristic impedance is 65. 7.3 PCI Bus Signal Specification This layout follows the PCI Rev. 2.1 Specification layout restrictions. The PCI SIG specification has stringent and detailed rules on decoupling, power consumption, trace length limits, routing, trace impedance, as well as signal loading. Therefore, it is essential to check the latest PCI specification before proceeding with new designs and layouts. The OC-12 Line Card conforms to the following PCI Specification/Recommendations: Component height on the component side does not exceed 0.570 inches, and on the solder side does not exceed 0.105 inches. PCI CLK signal trace is 2.5 inches +/- 0.1 inches and is connected to only one load.
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All 32-bit interface signals have the maximum trace length of 1.5 inches. Trace impedance for shared PCI signals are within 60 - 100 Ohm range, and trace velocity is between 150 and 190 ps/inch. 15 mil wide traces are used to connect the power and ground pins on PCI connector to their respective planes and the trace lengths are limited to 250 mil. 7.4 Routing All power and ground traces are as wide and as short as possible to minimize trace inductance. All high speed traces are routed over continuous image planes (power or ground planes). All traces carrying transmit and receive line rate data should be routed on the same side and kept as short as possible. Both signals of a differential pair should be of equal length and routed close to each other. 7.5 Emission Effective ways of reducing EMI include proper routing, de-coupling, power and ground distribution, shielding, and filtering. Most of the additional measurements listed below for EMI improvements also lend themselves towards improving system level performance. Data lines should be kept away from the clock signals to avoid noise coupling. Capacitor footprints can be placed along signals with fast rise and fall times. In the event that fast edges cause excessive EMI, installing these capacitors can slow them down. 7.6 Connectors
7.6.1 CompactPCI Connector The CompactPCI connector is defined as a 5 row by 47 position array of pins divided logically into two groups corresponding to the physical connector implementation. 32-bit PCI and connector keying is implemented on one connector (J1). An additional connector (J2) is defined for 64-bit transfers. In this design only 32-bit transfers are supported.
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The pinout of the CompactPCI connector is detailed in the CompactPCI specification [3]. J1 is used to supply power and ground to the board, as well as a 32-bit interface to the CPCI motherboard. LVDS data from the OC-12 Line Card is sent to the NSE over a custom section of the backplane. 7.6.2 OC-12 Optical Connector The Optical Transceiver converts incoming SONET OC-12 signals (622 Mb/s) to PECL levels for interfacing to the SPECTRA-622 (and vice versa in the transmit direction). The optical transceiver is mounted against the front panel allowing fiberoptic connectors on the cable to be plugged directly into the transceiver. 7.6.3 HS3 Connector AMP's Z-PACK HS3 connector is a two-piece board-to-board backplane connector. This high-density, high-speed connectors are modular devices with 25mm signal modules and half-size end modules with guide pins of six rows with 60 high-speed lines per 25mm, respectively. The Z-PACK HS3 connector has a controlled impedance of 50 and comes in dual microstrip configuration 7.6.4 RJ-45 Shielded Ethernet Connector AMP's (or Stewart's) RJ-45 shielded 8-pin female connector allows access to an onboard generic processor from a workstation via an ethernet connection. The pins are connected as follows Table 24 RJ-45 Shielded Ethernet Connector Pin Assignment
Pin 1 2 3 4 5 6 7 8 9 10 11 12 SIGNAL TX+ TXRX+ N/C N/C RXN/C N/C GND GND GND GND
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7.6.5 JTAG Debug Port The board supports in-system boundary scan testability through the use of the IEEE 1149.1 JTAG Debug Port. The devices are connected in the following order: * * * * * * * SPECTRA-622 TEMUX-84 #1 TEMUX-84 #2 TEMUX-84 #3 TEMUX-84 #4 SBS-Lite PCI9030 or generic onboard processor The pin assignment for the JTAG Debug Port is listed in Table 25. Table 25 JTAG Debug Port Pin Assignment
Pin 1 2 3 4 5 6 7 8 SIGNAL +3.3V TRST TMS TDO TDI TCK GND GND
7.6.6 CPLD ISP Port The CPLD can be reprogrammed in-circuit through the use of the IEEE 1149.1 JTAG interface. The CPLD is the only device attached to this port. The pin assignment for the CPLD ISP Port is listed in Table 26.
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Table 26
CPLD ISP Port Pin Assignment
Pin 1 2 3 4 5 6 7 8 SIGNAL +3.3V TRST TMS TDO TDI TCK GND GND
7.6.7 CPLD Clock SMB Connector The Clock SMB Connector is provided to allow the use of an external clock source to be distributed via the CPLD. The CPLD has access an external 77.76 MHz clock and 2 KHz framing pulse from an external source via SMB connectors. Jumpers have to be set in order to take advantage of the external signals. 7.6.8 MICTOR Connectors There are two high-density MICTOR 38-pin connectors used on the board. These connectors allow test equipment to connect directly into various busses so that signal activity can be easily monitored. The MICTOR connectors attached to the 77.76 MHz SBI336 Bus and the 77.76 MHz Telecom Bus. Please refer to the attached schematic in APPENDIX B: SCHEMATICS, for more details regarding which signals are available on each connector. 7.7 Jumper Configuration Jumpers are used on the Line Card to select certain software and hardware configuration options that require user selection. Jumpers are used when a feature only needs to be configured once at start-up to select a feature. Any feature that could require configuration changes more than once during card operation are mapped to a configuration register in the CPLD or on another device. On the line card a 8x2 header is used to act as jumper. When specified pins are connected and disconnected, as seen in the table below, features of the card can be altered. Table 27 show which features the jumpers on the OC-12 Line Card control and which pins on the header control these features.
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Table 27 Reference Designator J12 / J13
OC-12 Line Card Jumper Configuration Name JTAG Enable Operation To use the JTAG Debug Port, J14, to access the JTAG interface, there should be no jumpers on J14 and there must be a jumper on J9. To use the JTAG interface over the cPCI bus, J9 must be left unconnected, and a jumper must connect pins 4 and 5 of J14.
J10 (Header) Pin 1 & 2
Pin 3 & 4
Pin 5 & 6
Pin 7 & 8
Pin 9 & 10
Pin 11 & 12
The default setting for the outgoing frame pulse is using the incoming backplane frame pulse as the signal's source. When a jumper connects pins 1 and 2, the source of the frame pulse is the CPLD generated 2 kHz pulse. PCI9030 or The default setting is use of the external host Generic processor via the PCI9030 as the board's Processor microprocessor. Configuration When a jumper connects pins 3 and 4, the onboard processor is used as the board's microprocessor. 77MHz Clock The backplane 77.76 MHz Clock source will be Source 1 the default clock source. When a jumper connects pins 5 and 6, this indicates that the Local onboard 77.76 MHz oscillator will be the clock source. 77MHZ Clock The backplane 77.76 MHz Clock source will be Source 2 the default clock source. If a jumper connects pins 7 and 8, this indicates that the external 77.76 MHz clock source will be used. (the onboard oscillators overrides the external clock if both are activated) Frame Pulse The incoming backplane frame pulse will be the Source 1 default frame pulse source. When the jumper connects pins 9 and 10, this indicates that the locally generated frame pulse will be the frame pulse source. Frame Pulse The incoming backplane frame pulse will be the Source 2 default frame pulse source. When the jumper connects pins 11 and 12, this indicates that the external frame pulse source will be used.
Outgoing Frame Pulse Source
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Reference Designator Pin 13 & 14
Name
Operation (the locally generated frame pulse overrides the external frame pulse if both are activated) The backplane CMP signal is the default source that controls the connection memory of the SBS-Lite. When the jumper connects pins 13 and 14, this indicates that the SBS-Lite xCMP registers inside the CPLD generate the xCMP signals.
CMP Signal Source
When the jumpers on the header pins are unconnected the pin is set to a logic high (3.3V source). With a jumpers connected the CPLD pin is set to a logic low (GND). 7.8 LEDs Several LEDs will be used on the front panel to indicate the status of the SONET/SDH links and the status of the card power supply. See Table 28 below for a description of all status LEDs. Table 28 Function +5V Status (Vcc) +3.3V Status +1.8V Status Reset LOF (Loss of frame) LOS (Loss of signal) LRDI (Line remote defect indication) LAIS (Line alarm indication signal) SALM (Section alarm) LED Description Color Green Green Green Green Red Red Red Red Red Description Indicates when +5V supply is on. Indicates when +3.3V supply is on. Indicates when +1.8V supply is on. Indicates when RESET is asserted. Active when out of frame state persists for more than 3 ms. Active when a violating period (202.5us) of consecutive all zeroes is detected in the incoming stream. Active when line RDI is detected in the incoming stream. Active when line AIS is detected in the incoming stream. Active when any one of the alarms in the SPECTRA-622 Section Alarm Output Control #1 and #2 registers is active.
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RALM (Receive alarm) INTB (Interrupt) OOF (out of frame)
Red Red Red
Active when any of the alarms specified in the SPECTRA-622 RPPS RALM Output Control #1 and #2 are active. Active when the interrupt pin on any device is active. The OOF signal is high when the spectra622 is out of frame.
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8 8.1
SOFTWARE INTERFACES Memory Map The valid range of addressable registers is shown in Table 29. All other addresses are not used. Each device datasheet contains a list of all addressable registers for that device. The register address should be added to the lower address for each device in Table 29 to determine the actual address of that register on the card. Table 29 System Memory Map Local Address Range 00000h to 0FFFFh 10000h to 17FFFh 18000h to 1FFFFh 20000h to 27FFFh 28000h to 2FFFFh CS_2 CS_3 30000h to 3 31FFFh 32000h to 3FFFFh Device R/W Description SPECTRA-622 Registers TEMUX-84 Registers
PCI9030 Local Address Space CS_0 CS_1
(Individual TEMUX84 chip selects generated by CPLD)
SPECTRA-622 R/W TEMUX-84 #1 TEMUX-84 #2 TEMUX-84 #3 TEMUX-84 #4 SBS-Lite CPLD R/W R/W R/W
SBS-Lite Registers CPLD Registers
8.2
Address Mapping Within this reference design, there is a local bus on which a 16-bit device (SBSLite) and 8-bit devices (TEMUX-84 / SPECTRA-622) reside. Dealing with this constraint allowed for 2 possibilities. Using the PCI9030, one can dynamically interface a 32-bit PCI bus to 8-, 16-, and 32-bit local busses. While this option would have maximized memory efficiency on the CPU side, it also would have increased the design's complexity, both in hardware and in software.
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When the PCI9030 is activated, all the devices are assigned a 32-bit address space by the CPU. In the case of the 8-bit devices, the upper 24 bits of every CPU Lword are ignored. For the 16-bit device, half of all CPU Lwords are ignored. The major fault with this design choice is the waste of CPU memory. However, because the OC-12 Line Card does not require a large amount of memory space, this design choice is acceptable, considering the reduction in complexity it offers. Address translation works as follows: For a 32-bit local bus, the PCI9030 expects all addresses to be Lword (32-bit) aligned, causing all addresses to end with `00'. Because of this, the PCI9030 does not even provide the lowest 2 local address bits on the address bus. To accommodate this, every local address is mapped to a Lword aligned boundary on the CPU side. (i.e. register 0x0011 on the rd SPECTRA-622 is addressed as 0x001100 on the CPU side.) Because the 3 SPECTRA-622 register is mapped to the 12th CPU register, several CPU registers are unused. This corresponds to the ignored bits mentioned in the previous paragraph. 8.3 CPLD Operation The Xilinx XC95288XL High performance CPLD is chosen for its high pin count. One of the main functions of the CPLD is to mimic a large switch or multiplexer. The board has the ability to support two processor configurations, the external processor using the PCI9030 and generic onboard processor. On the CPLD, one pin (JUMPER_SIG) is set to determine which of the two is used. The JUMPER_SIG pin is set high (+3.3V) when the PCI9030 is used and low (grounded) when the onboard processor is used. The setting of this pin, controls many operations that the CPLD performs. All the I/O signals from the onboard processor and PCI9030 controller are routed into the CPLD. Depending on the settings of JUMPER_SIG, the CPLD will re-route these signals from one of the processors to all other devices on the board. The CPLD also determines which of the three 77.76 MHz clock and 2 kHz frame pulse sources is used by the devices. The local, external and backplane sources, are fed into the CPLD and one source is used as the 77.76 MHz timing master and one is used as the global frame pulse via the setting of specified jumpers. The OCMP and ICMP signal can also be retrieved from the backplane or generated onboard by the CPLD. Specified jumpers control these signals as well. See Table 27 for details on the jumper settings. . The PCI9030 will perform the address decoding for the four chip selects. Table 29 shows how the chip selects are mapped to the devices. The CPLD will use the TEMUX-84 chip select to enable one of the four TEMUX-84 devices
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depending on the selected address. Figure 42 shows the equivalent digital logic that is implemented inside of the CPLD. Figure 42 - CPLD Logic Diagram with PCI9030 Activated
LCLK SMB_INPUT Local 77.76 MHz OSC Ext. 77.76 MHz (SMB Input) BP 77.76 MHz Local generated FP Ext. FP (SMB Input) BP FP
Clock Section and Programmable Counter
2 kHz Framing Pulse 8 kHz Framing Pulse 77.76 MHz Clock Source
SBS-Lite FP Source
BP_CMP TEMUX4_INTB TEMUX3_INTB TEMUX2_INTB TEMUX1_INTB SBS_INTB SPECTRA_INTB
Internal Registers for Interrupt and Control signals
Data Bus D7 D6 D5 D4 D3 D2 D1 D0 ICMP OCMP
OUTPUT_INTB
RDB WRB
A18 A17 A16 A15 A1 A0
READYB
3.3V
JUMPER_SIG
(TEMUX-84 Enable)
CS1
A15 A14
Logic Decoding & 2-to-4 Demux with Tri-state enable
CS1A (TMX #1) CS1B (TMX #2) CS1C (TMX #3) CS1D (TMX #4)
ADDRESS BUS
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The READYB signal is held low because it is not required for the current memory access scheme. Reprogramming the CPLD could enable its use in the future. The CPLD will also contain logic for monitoring the interrupts that occur on the board. When an interrupt occurs, it will be stored into a register so that the host processor may read that register to determine the origin of the interrupt. This method simplifies interrupt handling because the host processor only needs to check one address to determine the location of the interrupt. Table 30 describes the function of each bit inside of the interrupt status register. The logical OR of all interrupt sources on the card is sent from the CPLD to the PCI9030, which is then sent over the PCI bus to the host processor. Table 30 CPLD Interrupt Status Register Bit # 31-6 5 4 3 2 1 0 R/W R R R R R R R Description 0 (Not Used) TEMUX-84 #4 Interrupt TEMUX-84 #3 Interrupt TEMUX-84 #2 Interrupt TEMUX-84 #1 Interrupt SBS-Lite Interrupt SPECTRA-622 Interrupt
Local Address 32000h 32000h 32000h 32000h 32000h 32000h 32000h
The CPLD contains a register called the SBS-Lite Control Register. This register contains bits that directly drive status lines on the SBS-Lite device. The ICMP and OCMP signal controls the selection of the connection memory page in the IMSU and OMSU (Memory Switch Unit), respectively. Table 31 shows the function of each bit inside of the SBS-Lite Control register. Table 31 SBS-Lite Control Register Bit # 31-3 2 1 0 R/W R R/W R/W R/W Description 0 (Not Used) CMP Control Mode OCMP ICMP
Local Address 32004h 32004h 32004h 32004h
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The SBS-Lite is comprised of two connection memory pages, page 0 and 1. The incoming and outgoing CMP (where CMP refers to either the ICMP or OCMP) signal determines which page is active. When the CMP control mode bit is set to 0, the CPLD drives the CMP signal with the value that is currently in the CMP bit. When the CMP control mode bit is set to 1, The connection memory page in the SBS-Lite is altered. Please refer to the SBS-Lite datasheet [ 7] for further details on the SBS-Lite functions.
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9
DISCLAIMER This document is a paper reference design, and as such, has not been built or tested as of this date. Please check the PMC-Sierra website regularly for updates to this document.
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10
REFERENCES 1. ANSI, "Synchronous Optical Network (SONET) Basic Description including Multiplex Structure, Rates, and formats", T1.105-1995. 2. PCIMG, "CompactPCI Hot Swap Specification", May 14, 1998, Draft R1.0 3. PCI Special Interest Group, "PCI Local Bus Specification Revision 2.1", Portland OR, June 1995. 4. PLX Technology, "PCI9030 Data Book", April 2000, Version 1.0 5. PMC-Sierra Inc., PMC-1981162, "SONET/SDH Payload Extractor/Aligner for 622 Mbits/s", September 2000, Issue 6. 6. PMC-Sierra Inc., PMC-1991437, "High Density 84 T1/63 E1 Framer with Integrated VT/TU Mappers and M13 Multiplexers Telecom Standard Product Data Sheet", October 2000, Issue 3. 7. PMC-Sierra Inc., PMC-2010883, "SBS-Lite Datasheet", Issue 1.
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11
APPENDIX A: BILL OF MATERIALS Table 32
REF DES
Major Components List
PART NUMBER NM93CS56LEN PCI9030-AA60PI PM8316 MANUFACTURER FAIRCHILD SEMI DESCRIPTION QTY 1 1 4 2048 BIT SERIAL EEPROM W/ DATA PROTECT AND SEQ READ DIP8 PLX TECHNOLOGY IC 3.3V PCI TARGET INTERFACE(32-BIT, 33MHZ, PQFP PACKAGE) PMC SIERRA IC HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX SIEMENS IC 3.3V DC/DC SINGLE MODE 1300NM 622MBD 1X9 TRANSCEIVER PMC-SIERRA SCALABLE BANDWIDTH SERIALIZER PMC-SIERRA SONET/SDH PAYLOAD EXTRACTOR/ALIGHNER FOR 622MBITS/S XILINX 3.3 V CPLD, 288 MICROCELLS, 192 I/O PINS
U2 U3 U8-U11
U12 U15 U18 U26
V23826-H18-C363 PM8611 PM5313 XC95288XL10BG256 I
1 1 1 1
Table 33
REF DES D3 U19 J14
Bill of Materials
MANUFACTURER VISHAY/LITE- ON TEXAS INSTRUMENTS AMP DESCRIPTION SURFACE MOUNT SWITCHING DIODE OCTAL BUFFER/DRIVER, 3-STATE OUTPUTS Z-PACK 6 ROW HS3 BACKPLANE CONNECTOR, RIGHT ANGLE RECEPTACLE MURATA NICKEL INNER ELECTRODE TYPE CAP METAL POLY PETP 100V 5% .047UF CAP CERAMIC X7R 0402 16V 0.01UF CAP CERAMIC X7R 0603 50V 0.01UF QTY 1 1 1
PART NUMBER 1N4148W SN74AHC540DW 120786-1
C22, C23, C25, C26, C29, C30 C106 C278, C279 C32, C33, C79, C93-C96, C104, C129, C131, C133, C135, C139, C143, C159, C160, C217, C243, C244, C246, C247 C19 C18 C1-C12, C14, C17, C24, C31, C34C78, C80-C87,
NEWARK -- 52F019 ? 2222 370 22473 ECU-E1C103KBQ ECU-V1H103KBV BC COMPONENTS PANASONIC PANASONIC
6 1 2 21
ECJ-1VB1E223K 08055C473JATN ECJ-1VB1C104K
PANASONIC AVX PANASONIC
CAP CERAMIC X7R 0603 25V 0.022UF CAP CERAMIC X7R 0850 50V 0.047UF CAP CERAMIC X7R 0603 16V 0.1UF
1 1 214
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
77
PRELIMINARY REFERENCE DESIGN PMC - 2001170 ISSUE 1
PM8316 TEMUX-84 PM8611 SBS-LITE
OC-12 LINE CARD REFERENCE DESIGN
C92, C97-C103, C105, C107-C128, C130, C132, C134, C136-C138, C140C142, C144-C154, C157, C158, C161C179, C190-C213, C218-C242, C245, C248-C267, C273, C276, C277 C16 C20, C21 C27, C28 C88-C91, C181, C269-C272, C274, C275 C155, C156 C180, C182-C189, C214-C216 C13, C15 C268 J3, J5 P1 J8 J4 J12, J13 J9 J2 J10 Q4, Q5 D1 U4 Q1, Q3 M1 J6
ECJ-3VB1C334K ECE-V1AA102P ECS-T1AD107R ECS-H1AC106R
PANASONIC PANASONIC PANASONIC PANASONIC
CAP CERAMIC X7R 1206 16V 0.33UF CAP ELECTRO VA SMD 10V 20% 1000UF CAP TANTALUM 10V 20% 100UF CAP TANCAPC 10V 20% 10UF
1 2 2 11
ECS-H1CD226R ECS-H1AD336R ECS-T0JY475R ECS-H0JD476R 2-767004-2 PART OF PCB DIGI-KEY -- A2100ND PZC36DAAN X 25/36 PZC36SAAN PZC36DAAN 53047-0310 PZC36DAAN IRL3502S PANASONIC LNG91LCFB LTC1422CS8
PANASONIC PANASONIC PANASONIC PANASONIC AMP PART OF PCB ? SULLINS SULLINS SULLINS MOLEX SULLIN INTERNATIONA L RECTIFIER ?
CAP TANCAPD 16V 20% 22UF CAP TANCAPD 10V 20% 33UF CAP TANCAPA 6.3V 20% 4.7UF CAP TANCAPD 6.3V 20% 47UF CONNECTOR 38 POS VERTICAL .025" TO .64" SMD MICTOR PART OF PCB COMPACT PCI ESD STRIP RIGHT ANGLE HEADER 25X2 GOLD 0.1" SPACING CONN HEADER 8 PIN CONN HEADER 2 ROW 0.1"X0.1" 2X16 PITCH HEADER - STRAIGHT SQUARE 3 ROW 1 POSITION/ROW HEADER 2X8 100 MIL 0.007 OHM, 20 V, HEXFET POWER MOSFET T-1 3/4 LED BLUE VERTICAL PCB MOUNT STATIC SENSITIVE HOT SWAP CONTROLLER GENERAL PURPOSE TRANSISTOR MOUNTING HOLE .150" DIA NANOENGINE SINGLE BOARD COMPUTER WITH MOLEX_7MM MATING CONNECTOR 2048 BIT SERIAL EEPROM W/ DATA PROTECT AND SEQ READ DIP8
2 12 2 1 2 1 1 1 2 1 1 1 2 1 1 2 1 1
U2
LINEAR TECHNOLOGY MMBT3904LT1 MOTOROLA MOUNTING HOLE N/A NANOENGINE/5348 BRIGHTSTAR 1- 1609 ENGINEERING/ MOLEX NM93CS56LEN FAIRCHILD SEMI
1
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
78
PRELIMINARY REFERENCE DESIGN PMC - 2001170 ISSUE 1
PM8316 TEMUX-84 PM8611 SBS-LITE
OC-12 LINE CARD REFERENCE DESIGN
Y2 Y3 Y6 Y7 Y4 Y1 SW1 U3 U1, U13, U14, U20, U23, U24 R40, R63 R24, R25, R61, R62 R31, R32 R12, R21, R34, R75, R76 R14 R16, R33, R35 R27, R29, R54, R135-R141 R10 R1-R3 R56, R57, R60 R20, R421, R422 R68 R81, R82 R38 R47 R17 R13 R83 R58, R59 R44, R46, R67, R69, R70, R94, R113, R604-R606, R608-R612 R52, R53 R4-R9, R11, R26, R28, R30, R39,
EH2645TS-37.056M ECLIPTEK EH2645TS-49.152M ECLIPTEK EH2620TTS77.760M EP2645TTS-44.736M EP2645TTS-51.840M CONNOR WINFIELD -- EE14-541 DIGIKEY -- P8009SND PCI9030-AA60PI PI49FCT3805CQ ERJ-6RQJR47V ERJ-3GSY0R00V WSL2512-R01-1 ERJ-3GSYJ102V ERJ-3GSYJ122V ERJ-3GSYJ100V ERJ-3GSYJ101V ERJ-3GSYJ104V ERJ-6GEYJ106V ERJ-3GSYJ150V ERJ-3GSYJ151V ERJ-3EKF2001V ERJ-3GSYJ2R2V ERJ-3EKF2431V ERJ-3GSYJ221V ERJ-3GSYJ271V ERJ-3GSYJ302V ERJ-3EKF3161V ERJ-6RQF3R3V ERJ-3GSYJ331V ECLIPTEK ECLIPTEK ECLIPTEK ? ?
OSCILLATOR 37.056MHZ 3.3V [TOL= 32PPM] [TEMP= 0-70C] [DUTY= 10%] OSCILLATOR 49.152MHZ 3.3V [TOL= 32PPM] [TEMP= 0-70C] [DUTY= 10%] OSCILLATOR 77.760MHZ 3.3V [TOL= 20PPM] [TEMP= 0-70C] [DUTY= 5%] OSCILLATOR, 44.736MHZ, 3.3V, 50PPM OSCILLATOR, 51.84MHZ, 3.3V, 50PPM 77.76 MHZ, LVPECL OSCILLATOR, 20 PPM, 3.3V VERT PCB MOUNT SPST PUSH BUTTOM
1 1 1 1 1 1 1 1 6 2 4 2 5 1 3 10 1 3 3 3 1 2 1 1 1 1 1 2 15
PLX TECHNOLOGY IC 3.3V PCI TARGET INTERFACE(32-BIT, 33MHZ, PQFP PACKAGE) PERICOM IC 3.3V 2X1:5 CMOS CLOCK DRIVER SPEED-GRADE-C QSOP20 PANASONIC RES 0805 1/10W 5% .47 OHM PANASONIC RES 0603 1/16W 5% ZERO OHM VISHAY PANASONIC PANASONIC PANASONIC PANASONIC PANASONIC PANASONIC PANASONIC PANASONIC PANASONIC PANASONIC PANASONIC PANASONIC PANASONIC PANASONIC PANASONIC PANASONIC PANASONIC RES 2512 1W 1% 0.01 OHM RES 0603 1/16W 5% 1.0K OHM RES 0603 1/16W 5% 1.2K OHM RES 0603 1/16W 5% 10 OHM RES 0603 1/16W 5% 100 OHM RES 0603 1/16W RES 0805 1/10W RES 0603 1/16W RES 0603 1/16W RES 0603 1/16W RES 0603 1/16W RES 0603 1/16W RES 0603 1/16W RES 0603 1/16W RES 0603 1/16W RES 0603 1/16W RES 0805 1/10W RES 0603 1/16W 5% 100K OHM 5% 10M OHM 5% 15 OHM 5% 150 OHM 5% 2.00K OHM 5% 2.2 OHM 1% 2.43K OHM 5% 220 OHM 5% 270 OHM 5% 3.0K OHM 1% 3.16K OHM 1% 3.3 OHM 5% 330 OHM
ERJ-3GSYJ4R7V ERJ-3GSYJ472V
PANASONIC PANASONIC
RES 0603 1/16W 5% 4.7 OHM RES 0603 1/16W 5% 4.7K OHM
2 33
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
79
PRELIMINARY REFERENCE DESIGN PMC - 2001170 ISSUE 1
PM8316 TEMUX-84 PM8611 SBS-LITE
OC-12 LINE CARD REFERENCE DESIGN
R41-R43, R45, R48-R51, R55, R64-R66, R89, R93, R95-R97, R111, R112, R119, R142, R271 R15, R18, R19, R22, R23, R71, R72 R84, R85 R37 R88 R36 RN1-RN13 RN233-RN23 8 RN18-RN25, RN40-RN42, RN48-RN53, RN55-RN60, RN62, RN63, RN66, RN79, RN86, RN87, RN90, RN91, RN94, RN95, RN119, RN120, RN136, RN139, RN140, RN147RN15 6, RN158, RN159, RN163, RN166-RN16 9, RN173, RN174, RN176, RN195, RN203, RN205RN20 8, RN215RN22 2 RN27 RN38, RN45, RN47, RN68RN72, RN74, RN77, RN78, RN80-RN85, RN88, RN89,
ERJ-3GEYJ470V
PANASONIC
47 OHM SINGLE RESISTOR
7
ERJ-3EKF49R9V ERJ-3EKF6811V ERJ-3EKF63R4V DIGI-KEY -PACT-ND PANASONIC -- EXBV8V100JV PANASONIC -- EXBV8V103JV DIGI-KEY -Y4ND
PANASONIC PANASONIC PANASONIC ? ? ? ?
RES 0603 1/16W 1% 49.9 OHM RES 0603 1/16W 1% 6.81K OHM RES 0603 1/16W 1% 63.4 OHM ? ? ? ?
2 1 1 1 13 6 72
PANASONIC -- EXB- ? V8V330JV DIGI-KEY -? Y4ND
? ?
1 82
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
80
PRELIMINARY REFERENCE DESIGN PMC - 2001170 ISSUE 1
PM8316 TEMUX-84 PM8611 SBS-LITE
OC-12 LINE CARD REFERENCE DESIGN
RN96-RN104 , RN108-RN11 3, RN116-RN11 8, RN124-RN13 1, RN137, RN138, RN157, RN160RN16 2, RN164, RN165, RN170RN17 2, RN175, RN177-RN18 3, RN185-RN18 8, RN197, RN204, RN211, RN224, RN228, RN265RN27 3 RN14-RN17, RN28-RN37, RN39, RN43, RN44, RN54, RN61, RN67, RN114, RN115, RN134, RN141, RN142, RN189RN19 3, RN196, RN199, RN232, RN239, RN248 RN26, RN73, RN75, RN76, RN105-RN10 7, RN133, RN135, RN143, RN212RN21 4, RN223, RN225, RN226 RN46, RN64, RN65, RN92, RN93, RN121RN12 3, RN132, RN144-RN14 6, RN184, RN194, RN198, RN200RN20 2, RN209, RN210 J7 U15 J11, J15 U18
PANASONIC -- EXB- ? V8V472JV
?
35
DIGI-KEY -? Y4ND
?
16
PANASONIC -EXB2HVR000V
?
?
20
STEWART OR AMP PM8611 903-499J-51P2 PM5313
? PMC-SIERRA AMPHENOL PMC-SIERRA
CONNECTOR SHIELDED RJ45 SCALABLE BANDWIDTH SERIALIZER SMB VERTICAL GOLD SONET/SDH PAYLOAD
1 1 2 1
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
81
PRELIMINARY REFERENCE DESIGN PMC - 2001170 ISSUE 1
PM8316 TEMUX-84 PM8611 SBS-LITE
OC-12 LINE CARD REFERENCE DESIGN
D2 D6, D7 U6 U8-U11
SSF-LXH5147LGD SSF-LXH5147LID TC74LVX08FN PM8316
LUMEX LUMEX TOSHIBA PMC SIERRA
U5
1.09E+08 LUCENT
U7
1.09E+08 LUCENT
U12 U26 J1
V23826-H18-C363 XC95288XL10BG256 I 352068-1
SIEMENS XILINX AMP
EXTRACTOR/ALIGHNER FOR 622MBITS/S LED QUAD GREEN HORIZONTAL LED QUAD RED HORIZONTAL IC HIGHSPEED CMOS QUAD 2 INPUT AND GATE SO14NB IC HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX TITANIA POWER MODULE, 3.3VDC AND 5.0VDC INPUT, 1.5VDC TO 3.3VDC OUTPUT 6A TITANIA POWER MODULE, 3.3VDC AND 5.0VDC INPUT, 1.5VDC TO 3.3VDC OUTPUT 6A IC 3.3V DC/DC SINGLE MODE 1300NM 622MBD 1X9 TRANSCEIVER 3.3 V CPLD, 288 MICROCELLS, 192 I/O PINS CONNECTOR ZPACK CPCI 2MM HM 110 POS. TYPE A WITH GND SHIELD
1 2 1 4
1
1
1 1 1
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
82
PRELIMINARY REFERENCE DESIGN PMC - 2001170 ISSUE 1
PM8316 TEMUX-84 PM8611 SBS-LITE
OC-12 LINE CARD REFERENCE DESIGN
12
APPENDIX B: SCHEMATICS
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
83
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE
PAGES 5 - 12 PAGES 3 - 4 SPECTRA622_BLOCK H TEMUX84_BLOCK SBS_BLOCK PAGE 13 H
REV
DESCRIPTION
DATE
APPR
AC1J1V1 APL AD<7..0> ADP PAGE 2 OPTICS G RXDP RXDN SD TXDP TXDN PECLV RXDP RXDN SD TXDP TXDN PECLV RXDP RXDN SD TXDP CTCLK<3..0> TXDN TEL_CLK<1..0> PECLV LAC1<3..0> F OUTPUT_INTB
AC1J1V1 APL AD<7..0> ADP
AC1J1V1 APL AD<7..0> ADP
SADATA<7..0> SADP SAV5 SAPL AJUST_REQ
SADATA<7..0> SADP SAV5 SAPL AJUST_REQ
SADATA<7..0> SADP SAV5 SAPL AJUST_REQ RPWRK RNWRK RPPROT RNPROT PAGE 18 LVDS_BLOCK
DD<7..0> DPL DC1J1V1 DDP
DD<7..0> DPL DC1J1V1 DDP
DD<7..0> DPL DC1J1V1 DDP SDDATA<7..0> SDDP SDV5 SDPL SAC1FP CTCLK<3..0> SREFCLK<4> LAC1<3..0> SDDATA<7..0> SDDP SDV5 SDPL SAC1FP SDDATA<7..0> SDDP SDV5 SDPL SAC1FP
RPWRK RNWRK RPPROT RNPROT
RPWRK RNWRK RPPROT RNPROT
G
TPWRK TNWRK TPPROT TNPROT RWSEL
TPWRK TNWRK TPPROT TNPROT RWSEL
TPWRK TNWRK TPPROT TNPROT RWSEL BP_CMP BP_FP BP_77M BP_77MOUT FPOUT F
OUTPUT_INTB
XCLK_T1<3..0> SDC1FP XCLK_E1<3..0> TEMUX_INTB<3..0> LREFCLK<3..0>
RC1FP IC1FP TC1FP
ADDR_B<12..0>
ADDR_A<13..0>
DATA_A<7..0>
SPECTRA_INTB
SPECTRA_CSB
RECVCLK<3..0>
DATA_B<7..0>
DS3_CLK<11..0> RSTB SREFCLK<3..0>
DATA_A<15..0>
ADDR_A<8..0>
SBS_INTB
TRSTB TCK TMS TDO_SPECTRA TDO_HDR
TRSTB TCK TMS TDO_SPECTRA
TEMUX_CSB<3..0>
DS3_REF<3..0>
TRSTB TRSTB TCK TCK TMS TMS TDO_TEMUX4 TDO_TEMUX4 TDO_SPECTRA RSTB
ICMP OCMP
TRSTB TCK TMS TDO_SBS TDO_TEMUX4 RSTB
TRSTB TCK TMS TDO_SBS
SBS_CSB
RDB
RDB
DFP
RDB
E E
WRB
WRB
<8..0>
DATA_A<7..0>
<7..0>
PAGE 19 PROCESSOR_INTERFACE D TRSTB TCK TMS TDO_PROC TDO_SBS ADDRN<17..0> DATAN<15..0> TRSTB TCK TMS CPLD
PAGES 14 - 15 SREFCLK<3..0> D
DFP ADDRN<17..0> DATAN<15..0> TCK TMS TDO_HDR TDO_PROC SPECTRA_CSB SPECTRA_INTB TEMUX_CSB<3..0> TEMUX_INTB<3..0> SBS_CSB SBS_INTB TCK TMS TDO_HDR TDO_PROC SPECTRA_CSB SPECTRA_INTB TEMUX_CSB<3..0> TEMUX_INTB<3..0> SBS_CSB SBS_INTB
WRBN RDBN CSB_0N CSB_1N OUTPUT_INTBN C READYBN LCLKN RSTBN PAGE 16 - 17 PCI_INTERFACE RSTBN TRSTB TCK TMS TDO_PROC TDO_SBS DATA_P<15..0> ADDR_P<17..0> RSTB_IN WRB_P RDB_P SBS_CSB_P SPECTRA_CSB_P OUTPUT_INTB_P TEMUX_IN_CSB_P CPLD_CSB_P READYB_P LCLK_P TRSTB_IN TRSTB TCK TMS RSTBN
WRBN RDBN CSB_0N CSB_1N OUTPUT_INTBN READYBN LCLKN
RSTB OUTPUT_INTB TEL_CLK<1..0> CTCLK<3..0> LAC1<3..0> XCLK_T1<3..0> XCLK_E1<3..0> LREFCLK<3..0> DS3_REF<3..0> RECVCLK<3..0> DS3_CLK<11..0> SREFCLK<4..0> SDC1FP RC1FP IC1FP TC1FP ADDR_A<13..0> DATA_A<15..0> ADDR_B<12..0> DATA_B<7..0> RDB WRB ICMP OCMP BP_CMP BP_FP BP_77M BP_77MOUT FPOUT
RSTB OUTPUT_INTB TEL_CLK<1..0> CTCLK<3..0> LAC1<3..0> XCLK_T1<3..0> XCLK_E1<3..0> LREFCLK<3..0> DS3_REF<3..0> RECVCLK<3..0> DS3_CLK<11..0> SREFCLK<4..0> SDC1FP RC1FP IC1FP TC1FP ADDR_A<13..0> DATA_A<15..0> ADDR_B<12..0> DATA_B<7..0> RDB WRB ICMP OCMP BP_CMP BP_FP BP_77M BP_77MOUT FPOUT
WRB
C
<3..0>
4
SREFCLK<4> B DRAWING OC12_LINECARD_ROOT OC12_LINECARD_ROOT LAST_MODIFIED=Wed May 23 16:46:16 2001
B
DATA_P<15..0> ADDR_P<17..0> RSTB_IN WRB_P RDB_P SBS_CSB_P SPECTRA_CSB_P OUTPUT_INTB_P TEMUX_IN_CSB_P CPLD_CSB_P READYB_P LCLK_P TRSTB_IN
PMC-Sierra, Inc.
DOCUMENT NUMBER: PMC-2001170 DOCUMENT ISSUE NUMBER: 1 TITLE: OC-12 LINE CARD ROOT DRAWING ENGINEER: PMC-SIERRA INC. (HS) ISSUE DATE: 2001/03/15 REVISION NUMBER: 1 PAGE:1 1 OF 19 A
A
10
9
8
7
6
5
4
3
2
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
G
G
3.3 V
2.2 0.01UF R81 22UF C155 0.1UF C157
C159
+
F
F 3.3 V
4.7K 2.2 22UF 0.1UF R82 C156 0.01UF
3.3 V
R89
PECLV\I
C158 C160
3C10<
+
6
E
8 7
U12
5
E
2 3 4 R94 R113 330 330 330 R70
VCCTX VCCRX TXD+ 3.3V RXD+ TXDRXDV23826-H18-C363 SD TXGND RXGND
9 1
RXDP\I RXDN\I SD\I
3D10< 3C10< 3D10<
TXDN\I D 3.3 V
49.9 R84 0.1UF C161 63.4 49.9 R85 R88
3C10>
D
TXDP\I C
3C10>
C
B DRAWING ABBREV=OPTICS TITLE=OPTICS LAST_MODIFIED=Mon May 28 11:42:54 2001
B
PMC-Sierra, Inc.
A DOCUMENT NUMBER: PMC-2001170 DOCUMENT ISSUE NUMBER: 1 TITLE: OC-12 LINE CARD OPTICAL TRANSCEIVER ENGINEER: PMC-SIERRA INC 10 9 8 7 6 5 4 3 2 ISSUE DATE: 2001/03/15 REVISION NUMBER: 1 PAGE:2 1 OF 19 A
10
9
8
7
6 3.3 V
0.1UF
5
4
3
2
1
REVISIONS
3.3 V
U18
SBGA
B18 C18 A18 D18 E18 C19 A20 B19 B20 C20 E19 B21 D19 D20 E20 C21 D21 A22 D26 B22 C22 B15 D15 E15 C15 A19 A15 A17 A14 B26
C248
DECOUPLING OF THE AHC540 DEVICE
C17 E17 D17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 B23 A24 E22 E23 B24 D23 A25 C23 C24 D24 E24 B25 D25 C25 A23 AL7 B17 C14 E14 B13 D14 E25 C26 B27 B14
ZONE
A1 A2 A3 A4 A1 A2 A3 A4
REV
U18
DESCRIPTION
SBGA
DATE
APPR
LED SSF-LXH5147
LED SSF-LXH5147
H RN185 RN182 RN181
RED D6
RED D7
TLRDI/TRCPFP RLAIS/TRCPCLK TLAIS/TRCPDAT
G
LOS/RRCPFP LAIS/RRCPDAT LRDI/RRCPCLK LOF TSLDCLK SALM TOWCLK RSLDCLK ROWCLK TSLD TSOW RSLD TSUC RSOW RSUC TLDCLK TOHCLK RLDCLK TLD ROHCLK TLOW RLD RLOW TOH SPECTRA622 TTOH ROH TTOHFP PM5313 RTOH TTOHCLK RTOHFP RX/TX RTOHCLK TTOHEN OVERHEAD TTOHREI PGMRCLK TCLK 3 OF 6 RCLK PGMTCLK RFPO TPOH RPOH TPOHFP RPOHFP TPOHCLK RPOHCLK RPOHEN TPOHEN TAD RALM RTCEN TAFP TACK RTCOH TPOHRDY B3E RAD
330
330
330
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
SOIC U19
AHC540
9 8 7 6 5 4 3 2
A7 A6 A5 A4 A3 A2 A1 A0
OE1
Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
OE2
11 12 13 14 15 16 17 18
100 100 100 100 100 100 100 100
R54 R135 R136 R137 R138 R139 R140 R141
RN45 RN45 RN47 RN47 RN47 RN47 RN68 RN68 RN68 RN68 RN69 RN69 RN69 RN69 RN70 RN70 RN70 RN70 RN71 RN71 RN71 RN71 RN72 RN72
3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2
6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7
330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330
AK25 AL25 AJ24 AK24 AL20 AH19 AK19 AL19 AJ14 AG14 AJ13 AK13 AJ27 AK27 AH26 AJ26 AH21 AJ21 AK21 AH20 AG15 AH15 AK15 AL15
19
1
DS3RICLK DS3TICLK<12> DS3ROCLK<12> DS3TICLK<11> DS3ROCLK<11> DS3TICLK<10> DS3ROCLK<10> DS3TICLK<9> DS3ROCLK<9> DS3TICLK<8> DS3ROCLK<8> DS3TICLK<7> DS3ROCLK<7> DS3TICLK<6> DS3ROCLK<6> DS3TICLK<5> DS3ROCLK<5> DS3TICLK<4> DS3ROCLK<4> DS3TICLK<3> DS3ROCLK<3> DS3TICLK<2> DS3ROCLK<2> DS3TICLK<1> DS3ROCLK<1> DS3TDAT<12> DS3RDAT<12> DS3TDAT<11> DS3RDAT<11> DS3TDAT<10> DS3RDAT<10> DS3TDAT<9> DS3RDAT<9> DS3TDAT<8> DS3RDAT<8> DS3TDAT<7> DS3RDAT<7> DS3TDAT<6> DS3RDAT<6> DS3TDAT<5> DS3RDAT<5> DS3TDAT<4> DS3RDAT<4> DS3TDAT<3> DS3RDAT<3> DS3TDAT<2> DS3RDAT<2> DS3TDAT<1> DS3 DS3RDAT<1>
PM5313
RN204
AL27 AL23 AJ22 AK22 AL22 AG17 AH17 AJ17 AK17 AH12 AH11 AJ11 AK11 AG22 AH23 AJ23 AK23 AK18 AJ18 AH18 AG18 AG12 AJ12 AK12 AL12 1 8
H
330
K1 K2 K3 K4
K1 K2 K3 K4
G
SPECTRA622
4 OF 6
TX_OVHD<25..1> 100MIL J4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49
F
E
U18
SBGA
330 330 330
P_1 P_3 P_5 P_7 P_9 P_11 P_13 P_15 P_17 P_19 P_21 P_23 P_25 P_27 P_29 P_31 P_33 P_35 P_37 P_39 P_41 P_43 P_45 P_47 P_49
P_2 P_4 P_6 P_8 P_10 P_12 P_14 P_16 P_18 P_20 P_22 P_24 P_26 P_28 P_30 P_32 P_34 P_36 P_38 P_40 P_42 P_44 P_46 P_48 P_50
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50
E31 AB31 U31 K30 E30 AB30 U30 K29 E29 AD30 W31 M28 G28 E13 D13 C13
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
AD<7..0>\I RX_OVHD<24..1> TEL_CLK<1..0>\I
3B5<
5F9>
6G9>
7G10> 8G10>
15F4>
DCK
F
1 0
SIGNAL IS INVERTED BY CPLD OUTPUT_INTB\I 14G9>
0 0 0
1 2 3
RN6416 RN6415 RN6414
APL\I AC1J1V1\I ADP\I
5E9> 5F9> 5E9>
6E9>
7E10> 8E10>
6E9>
7E10> 8E10>
ACK APL<4> APL<3> APL<2> APL<1> AC1J1V1/AFP<4> AC1J1V1/AFP<3> AC1J1V1/AFP<2> AC1J1V1/AFP<1> ADP<4> ADP<3> ADP<2> ADP<1> TPAISCK TPAISFP TPAIS
HEADER 25X2
E
RN197 RN186 RN186 RN186 RN185
RN185 RN183 RN183 RN183
RN182 RN182 RN181 RN181
RN180 RN180 RN197 RN180 RN162
T TFP
6 7 6 5 7
330 330 330 330 330
330 330 330 330
330 330 330 330
330 330 330 330 330
7 6 5 5 7
5 7 6 5
6 5 6 5
3.3 V
U18
R27 R29
AL10 AJ8 AK7 AJ10 AH10 AL9 AK9 AJ9 AH9 AL8 AK8 AK10 AG10 E26
SBGA
TDCK TC1J1V1/TFPO TPL TD<7> TD<6> TD<5> TD<4> TD<3> TD<2> TD<1> TD<0> TDP TFPI TFP
D
RN72 RN72 RN74
TP65
2E4> 2E4> 2E4> 2C4< 2D4< 2E4>
SD\I RXDP\I RXDN\I TXDP\I TXDN\I PECLV\I
50 OHMS 50 OHMS 50 OHMS 50 OHMS 50 OHMS 50 OHMS
LINE SIDE 2 OF 6 SCPI<3> SCPI<2> SCPI<1> SCPI<0> SCPO<1> SCPO<0> C0 TDREF2 TDREF1
DCK DPL<4> DPL<3> DPL<2> DPL<1> DC1J1V1<4> DC1J1V1<3> DC1J1V1<2> DC1J1V1<1> DMODE<1> DMODE<0> DDP<4> DDP<3> DDP<2> DDP<1> DPAISCK DPAISFP DPAIS DFP
4.7K 4.7K 4.7K 4.7K
M2 M1 U2 Y2 Y1 W1 W2 P2 P1 G2 R2 G3
REFCLK+ REFCLKSD RXD+ RXDRRCLK+ RRCLKTXD+ TXDPECLV PECLREF PREFEN C1
SPECTRA622 PM5313
ATP1 ATP0 PICLK PIN<7> PIN<6> PIN<5> PIN<4> PIN<3> PIN<2> PIN<1> PIN<0> FPIN OOF
L2 L3 AK4 AJ7 AH6 AJ6 AK6 AH5 AJ5 AK5 AL5 AH7 AH8
3.3 V
RN162 RN164 RN164 RN164 RN165 RN165 RN165 RN170 RN170 RN170 RN171 RN171 RN171 RN172 RN172 RN172 RN175 RN175 RN175 RN177 RN177 RN177 RN178 RN178 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0
4 2 3 4 2 3 4 2 3 4 2 3 4 2 3 4 2 3 4 2 3 4 2 3 1 2 3 4 5 6 7 8
5 330 7 330 6 330 5 330 7 330 6 330 5 330 7 330 6 330 5 330 7 330 6 330 5 330 7 330 6 330 5 330 7 330 6 330 5 330 7 330 6 330 5 330 7 330 6 330 16 RN46 15 RN46 14 RN46 13 RN46 12 RN46 11 RN46 10 RN46 9 RN46
AD31 AC28 AC29 AC30 AC31 AB27 AB28 AB29 V27 V28 V29 V30 V31 U27 U28 U29 M29 M30 M31 L28 L29 L30 K27 K28 G29 G30 G31 F27 F28 F29 F30 E28
AD<31> AD<30> AD<29> AD<28> AD<27> AD<26> AD<25> AD<24> AD<23> AD<22> AD<21> AD<20> AD<19> AD<18> AD<17> AD<16> AD<15> AD<14> AD<13> AD<12> AD<11> AD<10> AD<9> AD<8> AD<7> AD<6> AD<5> AD<4> AD<3> AD<2> AD<1> AD<0>
4.7K
R49
SPECTRA622 PM5313
SYSTEM 1 OF 6
DD<31> DD<30> DD<29> DD<28> DD<27> DD<26> DD<25> DD<24> DD<23> DD<22> DD<21> DD<20> DD<19> DD<18> DD<17> DD<16> DD<15> DD<14> DD<13> DD<12> DD<11> DD<10> DD<9> DD<8> DD<7> DD<6> DD<5> DD<4> DD<3> DD<2> DD<1> DD<0>
AG31 AF29 AF30 AE27 AE28 AE29 AE30 AE31 AA29 AA30 Y27 Y28 Y29 Y30 Y31 W27 P27 P28 P29 P30 P31 N27 N28 N29 J27 J28 J29 J30 J31 H27 H28 H29
3 2 3 4 2
2 3 4 4 2
4 2 3 4
3 4 3 4
3 4 1
6 5 8
D
100
100
0 0 0 0 0 0 0 0
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
RN198 7 RN198 6 RN198 5 RN198 4 RN198 3 RN198 2 RN198 1 RN198 0
330
C
3.3 V Y1
330
3.3 V
PLACE ALL DROP BUS SERIES RESISTORS NEAR THE SPECTRA-622 END OF THE BUS.
C
6 5 8 7
4.7K
0.01UF
.047UF
RN197
RN162
R68
C79
2.00K
RN36 RN36 RN37 RN37
7
GND
OUTN
1
3 4 1 2
14
8
C106
OSC_PECL PWR OUTP
R66
AH30 AD28 W29 N31 H31 AD27 W28 N30 H30 AH27 AG26 AF28 AA28 R28 K31 B12 A12 A13 AG29
V2 N1 P5
V1
E1 E2 F5 E3 E4 D2
DD<7..0>\I
4C1< 5E9< 8E10<
6E9<
7E10<
14G9>
DFP\I 0 DCK 0 0
4 5 6 13 12 11
77.76MHZ
20 PPM
RN64 RN64 RN64
DDP\I DC1J1V1\I DPL\I
4D1< 5E9< 8E10< 4D1< 5E9< 8E10< 4D1< 5E9< 8D10<
6E9< 6E9< 6E9<
7E10< 7E10< 7E10<
3F3>
3.3 V
R50 R65
330 330 330
330 330 330
330
330 330 330
330 330 330
B
14F10>
B DRAWING
5 7 6
4.7K
4.7K
13 12 11 10 9 8 7 6 5 4 3 2 1 0
D10 E10 A9 B9 C9 D9 E9 A8 B8 C8 D8 E8 A7 B7 B4 D5 B5 C5 A5
A<13> A<12> A<11> A<10> A<9> A<8> A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> TCK TMS TDI TDO TRSTB
PM5313
D<7> D<6> D<5> D<4> D<3> D<2> D<1> D<0> ALE CSB WRB/RWB RDB/E RSTB INTB MBEB
C12 D12 E12 B11 C11 D11 A10 B10 D7 C7 C6 B6 D6 C10 E7
DATA_A<7..0>\I
7 6 5 4 3 2 1 0
13C10<> 14E10<>
22 2 22 3 22 4 22 1 22 2 22 3 22 4 22 1
7 6 5 8 7 6 5 8
RN169 RN169 RN169 RN173 RN173 RN173 RN173 RN174
RN188 4 RN228 2 RN228 3
RN178 4 RN188 2 RN188 3
RN228 4
4 1 2
1 2 3
5 8 7
5 7 6
5
8 7 6
ADDR_A<13..0>\I
U18
SBGA
RN38 RN38 RN38
RN38 RN45 RN45
ABBREV=SPECTRA622_BLOCK TITLE=SPECTRA622_BLOCK LAST_MODIFIED=Mon May 28 11:42:17 2001
A
14A5> 14A5> 14A5> 5H9< 17C3>
TCK\I TMS\I TDO_HDR\I TDO_SPECTRA\I TRSTB\I
SPECTRA_CSB\I WRB\I RDB\I RSTB\I SPECTRA_INTB\I
14G9> 14G9> 14G9> 14F9> 14G9<
PMC-Sierra, Inc.
DOCUMENT NUMBER: PMC-2001170 DOCUMENT ISSUE NUMBER: 1 TITLE: OC-12 LINE CARD SPECTRA-622 SECTION ENGINEER: PMC-SIERRA (HS) ISSUE DATE: 2001/03/15 REVISION NUMBER: 1 PAGE:3 1 OF 19 A
SPECTRA622
JTAG/MICRO 5 OF 6
10
9
8
7
6
5
4
3
2
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
3.3 V 3.3 V
A1 A31 B2 B30 C3 C4 C16 C28 C29 D3 D4 D16 D28 D29 E5 E11 E16 E21 E27 L5 L27 T3 T4 T5 T27 T28 T29 AA5 AA27 AG5 AG11 AG16 AG21 AG27 AH3 AH4 AH16 AH28 AH29 AJ3 AJ4 AJ16 AJ28 AJ29 AK2 AK30 AL1 AL31
SPECTRA_POWER<18..0>
U18
4 5 0.1UF 47UF C263 C268 10UF C274 4.7 R52
SBGA
VDD<0> VDD<1> VDD<2> VDD<3> VDD<4> VDD<5> VDD<6> VDD<7> VDD<8> VDD<9> VDD<10> VDD<11> VDD<12> VDD<13> VDD<14> VDD<15> VDD<16> VDD<17> VDD<18> VDD<19> VDD<20> VDD<21> VDD<22> VDD<23> VDD<24> VDD<25> VDD<26> VDD<27> VDD<28> VDD<29> VDD<30> VDD<31> VDD<32> VDD<33> VDD<34> VDD<35> VDD<36> VDD<37> VDD<38> VDD<39> VDD<40> VDD<41> VDD<42> VDD<43> VDD<44> VDD<45> VDD<46> VDD<47>
+
+
G
3.3 V
C264
+
R75 1.0K R76
E6 AK28 W4 M5 Y4 R4 V3 L4 V4 K1
VBIAS<1> VBIAS<0> PBIAS<3> PBIAS<2> PBIAS<1> PBIAS<0> QAVD<1> QAVD<0> QAVS<1> QAVS<0> SAVS<7> SAVS<6> SAVS<5> SAVS<4> SAVS<3> SAVS<2> SAVS<1> SAVS<0>
C275
+
1.0K
AVD<18> AVD<17> AVD<16> AVD<15> AVD<14> AVD<13> AVD<12> AVD<11> AVD<10> AVD<9> AVD<8> AVD<7> AVD<6> AVD<5> AVD<4> AVD<3> AVD<2> AVD<1> AVD<0> AVS<18> AVS<17> AVS<16> AVS<15> AVS<14> AVS<13> AVS<12> AVS<11> AVS<10> AVS<9> AVS<8> AVS<7> AVS<6> AVS<5> AVS<4> AVS<3> AVS<2> AVS<1> AVS<0>
P3 N2 W3 W5 M4 M3 K5 K3 H2 J4 J2 AD3 AC5 AC4 U5 AB5 AB4 AB1 AA2 R5 P4 V5 Y3 N4 N5 J1 K4 J5 H1 J3 AD2 AD1 AC3 U4 AC2 AC1 AB2 AA3
18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
G
8 0.1UF 10UF C269 10UF
4.7 R53
9 0.1UF 10UF
15 R56
F
0.1UF 0.1UF
C265
C107
C108
AB3 AA4 Y5 U1 R1 R3 N3 K2
POWER 6 OF 6
C270
SPECTRA622 PM5313
F +
10 0.1UF 10UF
15 R57 C266 C271
E
+
VSS<0> VSS<1> VSS<2> VSS<3> VSS<4> VSS<5> VSS<6> VSS<7> VSS<8> VSS<9> VSS<10> VSS<11> VSS<12> VSS<13> VSS<14> VSS<15> VSS<16> VSS<17> VSS<18> VSS<19> VSS<20> VSS<21> VSS<22> VSS<23> VSS<24> VSS<25> VSS<26> VSS<27> VSS<28> VSS<29> VSS<30> VSS<31> VSS<32> VSS<33> VSS<34> VSS<35> VSS<36> VSS<37> VSS<38> VSS<39> VSS<40> VSS<41> VSS<42> VSS<43> VSS<44> VSS<45> VSS<46> VSS<47> VSS<48> VSS<49> VSS<50> VSS<51> VSS<52> VSS<53> VSS<54> VSS<55>
E
12 11 0.01UF 10UF C272 15 R60 C143
A2 A3 A4 A6 A11 A16 A21 A26 A28 A29 A30 B1 B3 B16 B29 B31 C1 C2 C30 C31 D1 D31 F1 F31 L1 L31 T1 T2 T30 T31 AA1 AA31 AF1 AF31 AH1 AH31 AJ1 AJ2 AJ30 AJ31 AK1 AK3 AK16 AK29 AK31 AL2 AL3 AL4 AL6 AL11 AL16 AL21 AL26 AL28 AL29 AL30
+
SPECTRA-622 TO TEMUX-84S TELECOM BUS
J5
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37
2-767004-2
SCL DSA B-CLK B-D15 B-D14 B-D13 B-D12 B-D11 B-D10 B-D9 B-D8 B-D7 B-D6 B-D5 B-D4 B-D3 B-D2 B-D1 B-D0
MICTOR 38 PIN
+5V GND_D A-CLK A-D15 A-D14 A-D13 A-D12 A-D11 A-D10 A-D9 A-D8 A-D7 A-D6 A-D5 A-D4 A-D3 A-D2 A-D1 A-D0
D
14C10> 15F4> 5F9> 8E10> 7E10> 6E9>5E9> 8E10> 7E10> 6E9>5E9>
CTCLK<0>\I TEL_CLK<0>\I AC1J1V1\I ADP\I APL\I
7 6 5 4 3 2 1 0
DECOUPLING FOR SPECTRA-622. PLACE ONE 0.1UF CAP AS CLOSE AS POSSIBLE TO EACH VDD PIN
3.3 V
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38
D LAC1<0>\I TEL_CLK<1>\I DC1J1V1\I DDP\I DPL\I
7 6 5 4 3 2 1 0
14C10> 15F4> 3B1> 3B1> 3B1>
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
C110
C116
C121
C127
C147
C150
C153
0.1UF
C138
C144
C252
7G10> 5F9> 8G10> 6G9>
AD<7..0>\I
DD<7..0>\I
3C1>
C80
C
C83
39 40 41 42 43
3.3 V
DECOUPLING FOR SPECTRA-622. PLACE ONE 0.1UF CAP AS CLOSE AS POSSIBLE TO EACH OF THE ANALOG AVD PINS (FOR THE ONES THAT AREN'T ALREADY DECOUPLED)
0.1UF 0.1UF
C
3.3 V
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
C109
C111
C113
C115
C117
C119
C126
0.1UF
C122
C124
C128
C130
C132
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
C255
C256
C257
C258
C259
C260
C267
C273
C276
0.1UF
C261
C262
3.3 V B B
C253
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
C140
C145
C112
C118
C123
C134
C148
C151
C154
C81
C84
DECOUPLING CAPS PLACED FOR 3.3V BIASING PINS 3.3 V
C277
DRAWING SPECTRA622_BLOCK SPECTRA622_BLOCK LAST_MODIFIED=Mon May 28 11:42:22 2001
3.3 V
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
C142
C146
C249
0.1UF
C105
C114
C120
C125
C136
C149
C152
C251
C254
C82
C250
PMC-Sierra, Inc.
DOCUMENT NUMBER: PMC-2001170 DOCUMENT ISSUE NUMBER: 1 TITLE: OC-12 LINE CARD SPECTRA POWER / CONNECTORS ENGINEER: PMC-SIERRA (HS) ISSUE DATE: 2001/03/15 REVISION NUMBER: 1 PAGE:4 1 OF 19 A
A
10
9
8
7
6
5
4
3
2
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
JTAG INTERFACE
17C3> 6H9< 3A10> 14A5> 14A5>
H
TRSTB\I TDO_TEMUX1 TDO_SPECTRA\I TMS\I TCK\I
CTCLK<0>\I G
14C10> 15E4>
TELECOM BUS
15F4> 14C10>
SREFCLK<0>\I
G
LREFCLK<0>\I LAC1<0>\I
3.3 V RN396 PBGA U8 4.7K
TEMUX#1
TCK TMS TDI TDO TRSTB
B1 D2 E3 D1 C1 F19 C10
F
3F1< 4D3< 3F1< 8G10> 7G10> 6G9> 4C3<
AC1J1V1\I AD<7..0>\I
7 6 5 4 3 2 1 0
22 22 22 22 22 22 22 22 22 22 22
7 6 5 4 3 2 1 0
3 4 1 2 3 4 1 2 3 4 1 7 8 1 2 3 4 5 6 7 8 1
6 5 8 7 6 5 8 7 6 5 8
RN203 RN203 RN205 RN205 RN205 RN205 RN206 RN206 RN206 RN206 RN207
Y4 AA4 W10 AA11 AB11 W11 W12 AA12 W13 AB13 AA13 Y13 W14 AB14 AA14 W15 AB3 AB4 AA5 Y6 Y3 AB5 AA6 W5 Y7 AB6 AB7 W6 Y8 AA8 Y21 Y22 W22 U20 U21 V19 T20 U22 AA16 Y16 W18 AA17 AB18 W19 AA18 AB20 AA19 AA20 Y19 AA21 AB22 T21 AA15 W17 AB16 W20 AA22
TEMUX-84 PM8316 1 of 4 LREFCLK L77 LAC1 LAC1J1V1 LAOE LADATA7 LADATA6 LADATA5 LADATA4 LADATA3 LADATA2 LADATA1 LADATA0 LADP LAPL LAV5 LDDATA7 LDDATA6 LDDATA5 LDDATA4 LDDATA3 LDDATA2 LDDATA1 LDDATA0 LDDP LDC1J1V1 LDPL LDV5 LDTPL LDAIS D7 D6 D5 D4 D3 D2 D1 D0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 INTB CSB RDB WRB RSTB ALE TEL-SBI
3
F
CTCLK SREFCLK
4D3< 4D3<
3E1< 3F1<
8E10> 7E10> 6E9> 8E10> 7E10> 6E9> 3C1>
ADP\I APL\I DD<7..0>\I
E
0 0 0 0 0 0 0 0 0 0 0
10 RN64 9 RN64 16 RN65 15 RN65 14 RN65 13 RN65 12 RN65 11 RN65 10 RN65 9 RN65 16 RN92
E
3B1> 3B1> 3B1>
DDP\I DC1J1V1\I DPL\I 330 330 330
RN197
330
RN204
RN204
D
RN204
7 6 5 4 3 2 1 0
22 1 22 2 22 3 22 4 22 1 22 2 22 3 22 4
8 7 6 5 8 7 6 5
RN139 RN139 RN139 RN139 RN140 RN140 RN140 RN140
12 11 10 9 8 7 6 5 4 3 2 1 0
D
3.3 V
4.7K
C
R42
C
MICROPROCESSOR INTERFACE
14D10<> 8B10<> 7B10<> 6B9<> 14D10> 14G9< 14G9> 14G9> 14G9> 14F9>
DATA_B<7..0>\I ADDR_B<12..0>\I TEMUX_INTB<0>\I TEMUX_CSB<0>\I RDB\I WRB\I RSTB\I TEMUX84_BLOCK TEMUX84_BLOCK LAST_MODIFIED=Mon May 28 11:42:25 2001 DRAWING B
B
PMC-Sierra, Inc.
A DOCUMENT NUMBER: PMC-2001170 DOCUMENT ISSUE NUMBER: 1 TITLE: OC-12 LINE CARD TEMUX-84 #1 TELECOM / MICRO ENGINEER: PMC-SIERRA (HS) 10 9 8 7 6 5 4 3 2 ISSUE DATE: 2001/03/15 REVISION NUMBER: 1 PAGE:5 1 OF 19 A
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
JTAG INTERFACE
17C3> 7H10< 5H9> 14A5> 14A5>
H
TRSTB\I TDO_TEMUX2 TDO_TEMUX1 TMS\I TCK\I
CTCLK<1>\I G
14C10> 15E4>
TELECOM BUS
15F4> 14C10> 4C3< 3F1< 8G10> 7G10> 5F9>
SREFCLK<1>\I
G
LREFCLK<1>\I LAC1<1>\I AD<7..0>\I 3.3 V 4.7K
PBGA U9
TEMUX#2
TCK TMS TDI TDO TRSTB
B1 D2 E3 D1 C1 F19 C10
F
Y4 AA4 W10 AA11 AB11 7 6 5 4 3 2 1 0
TEMUX-84 PM8316 1 of 4 LREFCLK L77 LAC1 LAC1J1V1 LAOE LADATA7 LADATA6 LADATA5 LADATA4 LADATA3 LADATA2 LADATA1 LADATA0 LADP LAPL LAV5 LDDATA7 LDDATA6 LDDATA5 LDDATA4 LDDATA3 LDDATA2 LDDATA1 LDDATA0 LDDP LDC1J1V1 LDPL LDV5 LDTPL LDAIS D7 D6 D5 D4 D3 D2 D1 D0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 INTB CSB RDB WRB RSTB ALE TEL-SBI
RN43
F
22 1 22 2 22 3 22 4 22 1 22 2 22 3 22 4 22 1 22 2
8 7 6 5 8 7 6 5 8 7
RN48 RN48 RN48 RN48 RN49 RN49 RN49 RN49 RN50 RN50
W11 W12 AA12 W13 AB13 AA13 Y13 W14 AB14 AA14 W15 AB3 AB4 AA5 Y6 Y3 AB5 AA6 W5 Y7 AB6 AB7 W6 Y8 AA8 Y21 Y22 W22 U20 U21 V19 T20 U22 AA16 Y16 W18 AA17 AB18 W19 AA18 AB20 AA19 AA20 Y19 AA21 AB22 T21 AA15 W17 AB16 W20 AA22
CTCLK SREFCLK
4D3< 4D3<
3E1< 3F1<
8E10> 7E10> 5E9> 8E10> 7E10> 5E9> 3C1>
ADP\I APL\I DD<7..0>\I
7 6 5 4 3 2 1 0
E
0 0 0 0 0 0 0 0 0 0 0
2 3 4 5 6 7 8 1 2 3 4
15 RN92 14 RN92 13 RN92 12 RN92 11 RN92 10 RN92 9 RN92 16 RN93 15 RN93 14 RN93 13 RN93
E
3B1> 3B1> 3B1>
DDP\I DC1J1V1\I DPL\I 330 330 330
RN211
RN211
D
RN211
7 6 5 4 3 2 1 0
22 3 22 4 22 1 22 2 22 3 22 4 22 1 22 2
6 5 8 7 6 5 8 7
RN147 RN147 RN148 RN148 RN148 RN148 RN149 RN149
12 11 10 9 8 7 6 5 4 3 2 1 0
D
3.3 V
4.7K
C
R45
C
MICROPROCESSOR INTERFACE
14D10<> 8B10<> 7B10<> 5B9<> 14D10> 14G9< 14G9> 14G9> 14G9> 14F9>
DATA_B<7..0>\I ADDR_B<12..0>\I TEMUX_INTB<1>\I DRAWING TEMUX_CSB<1>\I RDB\I WRB\I RSTB\I TEMUX84_BLOCK TEMUX84_BLOCK LAST_MODIFIED=Mon May 28 11:42:27 2001 B
B
PMC-Sierra, Inc.
A DOCUMENT NUMBER: PMC-2001170 DOCUMENT ISSUE NUMBER: 1 TITLE: OC-12 LINE CARD TEMUX-84 #2 TELECOM / MICRO ENGINEER: PMC-SIERRA (HS) 10 9 8 7 6 5 4 3 2 ISSUE DATE: 2001/03/15 REVISION NUMBER: 1 PAGE:6 1 OF 19 A
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
JTAG INTERFACE
17C3> 8H10< 6H9> 14A5> 14A5>
TRSTB\I TDO_TEMUX3 TDO_TEMUX2 TMS\I TCK\I
CTCLK<2>\I SREFCLK<2>\I G
14C10> 15E4>
TELECOM BUS
15F4> 14C10> 4C3< 3F1< 8G10> 6G9> 5F9>
G
LREFCLK<2>\I LAC1<2>\I AD<7..0>\I 3.3 V PBGA U10 4.7K
TEMUX#3
TCK TMS TDI TDO TRSTB
B1 D2 E3 D1 C1 F19 C10
RN54
8
F
Y4 AA4 W10 AA11 AB11 7 6 5 4 3 2 1 0
TEMUX-84 PM8316 1 of 4 LREFCLK L77 LAC1 LAC1J1V1 LAOE LADATA7 LADATA6 LADATA5 LADATA4 LADATA3 LADATA2 LADATA1 LADATA0 LADP LAPL LAV5 LDDATA7 LDDATA6 LDDATA5 LDDATA4 LDDATA3 LDDATA2 LDDATA1 LDDATA0 LDDP LDC1J1V1 LDPL LDV5 LDTPL LDAIS D7 D6 D5 D4 D3 D2 D1 D0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 INTB CSB RDB WRB RSTB ALE TEL-SBI
1
F
22 4 22 1 22 2 22 3 22 4 22 1 22 2 22 3 22 4 22 1
5 8 7 6 5 8 7 6 5 8
RN53 RN55 RN55 RN55 RN55 RN56 RN56 RN56 RN56 RN57
W11 W12 AA12 W13 AB13 AA13 Y13 W14 AB14 AA14 W15 AB3 AB4 AA5 Y6 Y3 AB5 AA6 W5
CTCLK SREFCLK
4D3< 4D3<
3E1< 3F1<
8E10> 6E9> 5E9> 8E10> 6E9> 5E9> 3C1>
ADP\I APL\I DD<7..0>\I
7 6 5 4 3 2 1 0
E
0 0 0 0 0 0 0 0 0 0 0
5 6 7 8 1 2 3 4 5 6 7
12 RN93 11 RN93 10 RN93 9 RN93 16 RN144 15 RN144 14 RN144 13 RN144
E
3B1> 3B1> 3B1>
DDP\I DC1J1V1\I DPL\I
12 RN144 Y7 11 RN144 AB6 10 RN144 AB7 W6 Y8 AA8 5 8 7 6 5 8 7 6
D RN211 RN224 RN224
7 6 5 4 3 2 1 0
22 4 22 1 22 2 22 3 22 4 22 1 22 2 22 3
RN152 RN153 RN153 RN153 RN153 RN154 RN154 RN154
12 11 10 9 8 7 6 5 4 3 2 1 0
Y21 Y22 W22 U20 U21 V19 T20 U22 AA16 Y16 W18 AA17 AB18 W19 AA18 AB20 AA19 AA20 Y19 AA21 AB22 T21 AA15 W17 AB16 W20 AA22
330
330
330
D
3.3 V
4.7K
C
R48
C
MICROPROCESSOR INTERFACE
14D10<> 8B10<> 6B9<> 5B9<> 14D10> 14G9< 14G9> 14G9> 14G9> 14F9>
DATA_B<7..0>\I ADDR_B<12..0>\I TEMUX_INTB<2>\I TEMUX_CSB<2>\I RDB\I WRB\I RSTB\I DRAWING TEMUX84_BLOCK TEMUX84_BLOCK LAST_MODIFIED=Mon May 28 11:42:29 2001 B
B
PMC-Sierra, Inc.
A DOCUMENT NUMBER: PMC-2001170 DOCUMENT ISSUE NUMBER: 1 TITLE: OC-12 LINECARD TEMUX-84 #3 TELECOM / MICRO ENGINEER: 10 9 8 7 6 5 4 3 PMC-SIERRA (HS) 2 ISSUE DATE: 2001/03/15 REVISION NUMBER: 1 PAGE:7 1 OF 19 A
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
JTAG INTERFACE
17C3> 13B5< 7H10> 14A5> 14A5>
TRSTB\I TDO_TEMUX4\I TDO_TEMUX3 TMS\I TCK\I CTCLK<3>\I SREFCLK<3>\I
14C10> 15E4>
G
TELECOM BUS
15F4> 14C10> 4C3< 3F1< 7G10> 6G9> 5F9>
G
LREFCLK<3>\I LAC1<3>\I AD<7..0>\I
3.3 V RN617 4.7K PBGA U11
TEMUX#4
TCK TMS TDI TDO TRSTB
B1 D2 E3 D1 C1 F19 C10
2
F
Y4 AA4 W10 AA11 AB11 7 6 5 4 3 2 1 0
TEMUX-84 PM8316 1 of 4 LREFCLK L77 LAC1 LAC1J1V1 LAOE LADATA7 LADATA6 LADATA5 LADATA4 LADATA3 LADATA2 LADATA1 LADATA0 LADP LAPL LAV5 LDDATA7 LDDATA6 LDDATA5 LDDATA4 LDDATA3 LDDATA2 LDDATA1 LDDATA0 LDDP LDC1J1V1 LDPL LDV5 LDTPL LDAIS D7 D6 D5 D4 D3 D2 D1 D0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 INTB CSB RDB WRB RSTB ALE TEL-SBI
F
22 3 22 4 22 1 22 2 22 3 22 4 22 1 22 2 22 3 22 4
6 5 8 7 6 5 8 7 6 5
RN60 RN60 RN62 RN62 RN62 RN62 RN63 RN63 RN63 RN63
W11 W12 AA12 W13 AB13 AA13 Y13 W14 AB14 AA14 W15 AB3 AB4 AA5 Y6 Y3 AB5 AA6 W5
CTCLK SREFCLK
4D3< 4D3<
3E1< 3F1<
7E10> 6E9> 5E9> 7E10> 6E9> 5E9> 3C1>
ADP\I APL\I DD<7..0>\I
7 6 5 4 3 2 1 0
E
0 0 0 0 0 0 0 0 0 0 0
8 1 2 3 4 5 6 7 8 1 2
9 RN144 16 RN145 15 RN145 14 RN145 13 RN145 12 RN145 11 RN145 10 RN145
E
3B1> 3B1> 3B1>
DDP\I DC1J1V1\I DPL\I
Y7 9 RN145 16 RN146 AB6 15 RN146 AB7 W6 Y8 AA8 8 7 6 5 8 7 6 5
330
330
330
D RN224 RN224 RN228
7 6 5 4 3 2 1 0
22 1 22 2 22 3 22 4 22 1 22 2 22 3 22 4
RN158 RN158 RN158 RN158 RN159 RN159 RN159 RN159
12 11 10 9 8 7 6 5 4 3 2 1 0
Y21 Y22 W22 U20 U21 V19 T20 U22
D
3.3 V
AA16 Y16 W18 AA17 AB18 W19 AA18 AB20 AA19 AA20 Y19 AA21 AB22 T21 AA15 W17 AB16 W20 AA22
4.7K
C
R51
C
MICROPROCESSOR INTERFACE
14D10<> 7B10<> 6B9<> 5B9<> 14D10> 14G9< 14G9> 14G9> 14G9> 14F9>
DATA_B<7..0>\I ADDR_B<12..0>\I TEMUX_INTB<3>\I TEMUX_CSB<3>\I RDB\I WRB\I RSTB\I DRAWING TEMUX84_BLOCK TEMUX84_BLOCK LAST_MODIFIED=Mon May 28 11:42:31 2001 B
B
PMC-Sierra, Inc.
A DOCUMENT NUMBER: PMC-2001170 DOCUMENT ISSUE NUMBER: 1 TITLE: OC-12 LINE CARD TEMUX-84 #4 TELECOM / MICRO ENGINEER: PMC-SIERRA (HS) 10 9 8 7 6 5 4 3 2 ISSUE DATE: 2001/03/15 REVISION NUMBER: 1 PAGE:8 1 OF 19 A
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE
9D3>
REV
DESCRIPTION
DATE
APPR
TEMUX_PULLDOWN4<20..0> H
H
9D5> 9D8> 9D10>
TEMUX_PULLDOWN3<20..0>
TEMUX_PULLDOWN2<20..0> PBGA U10 PBGA U9 PBGA U8 TEMUX#4 TEMUX-84 PM8316 2 of 4 RGAPCLK/RSCLK3 RGAPCLK/RSCLK2 RGAPCLK/RSCLK1 RDATO3 RDATO2 RDATO1 RFPO/RMFPO3 RFPO/RMFPO2 RFPO/RMFPO1 ROVRHD3 ROVRHD2 ROVRHD1 TFPO/TMFPO/TGAPCLK3 TFPO/TMFPO/TGAPCLK2 TFPO/TMFPO/TGAPCLK1 TDATI3 TDATI2 TDATI1 TFPI/TMFPI3 TFPI/TMFPI2 TFPI/TMFPI1
TEMUX_PULLDOWN1<20..0> PBGA TEMUX#1 U11 TEMUX-84 PM8316 2 of 4 P1 14 RGAPCLK/RSCLK3 RCLK3 T1 13 RGAPCLK/RSCLK2 RCLK2 Y1 12 RGAPCLK/RSCLK1 RCLK1
11 10 9 P2 U1 V3 P3 T3 W2 R3 V1 W3 R2 U2 AA1 U4 W1 AB1 T4 V4 Y2
TEMUX#2 TEMUX-84 PM8316 2 of 4 RGAPCLK/RSCLK3 RGAPCLK/RSCLK2 RGAPCLK/RSCLK1 RDATO3 RDATO2 RDATO1 RFPO/RMFPO3 RFPO/RMFPO2 RFPO/RMFPO1 ROVRHD3 ROVRHD2 ROVRHD1 TFPO/TMFPO/TGAPCLK3 TFPO/TMFPO/TGAPCLK2 TFPO/TMFPO/TGAPCLK1 TDATI3 TDATI2 TDATI1 TFPI/TMFPI3 TFPI/TMFPI2 TFPI/TMFPI1
TEMUX#3 TEMUX-84 PM8316 2 of 4 RGAPCLK/RSCLK3 RGAPCLK/RSCLK2 RGAPCLK/RSCLK1 RDATO3 RDATO2 RDATO1 RFPO/RMFPO3 RFPO/RMFPO2 RFPO/RMFPO1 ROVRHD3 ROVRHD2 ROVRHD1 TFPO/TMFPO/TGAPCLK3 TFPO/TMFPO/TGAPCLK2 TFPO/TMFPO/TGAPCLK1 TDATI3 TDATI2 TDATI1 TFPI/TMFPI3 TFPI/TMFPI2 TFPI/TMFPI1
H4 L3 N3 H2 K4 N2 H1 K2 M2 H3 K1 N1 F4 J4 M3 G2 J3 L2 G1 J1 M1 15 16 17 18 19 20
14 13 12 11 10 9 8 7 6
P1 T1 Y1 P2 U1 V3 P3 T3 W2 R3 V1 W3 R2 U2 AA1 U4 W1 AB1 T4 V4 Y2
RCLK3 RCLK2 RCLK1 RPOS/RDAT3 RPOS/RDAT2 RPOS/RDAT1 RNEG/RLCV3 RNEG/RLCV2 RNEG/RLCV1 TCLK3 TCLK2 TCLK1 TPOS/TDAT3 TPOS/TDAT2 TPOS/TDAT1 TNEG/TMFP3 TNEG/TMFP2 TNEG/TMFP1 TICLK3 TICLK2 TICLK1
H4 L3 N3 H2 K4 N2 H1 K2 M2 H3 K1 N1 F4 J4 M3 G2 15 J3 16 L2 17 G1 18 J1 19 M1 20
14 13 12 11 10 9 8 7 6
P1 T1 Y1 P2 U1 V3 P3 T3 W2 R3 V1 W3 R2 U2 AA1 U4 W1 AB1 T4 V4 Y2
RCLK3 RCLK2 RCLK1 RPOS/RDAT3 RPOS/RDAT2 RPOS/RDAT1 RNEG/RLCV3 RNEG/RLCV2 RNEG/RLCV1 TCLK3 TCLK2 TCLK1 TPOS/TDAT3 TPOS/TDAT2 TPOS/TDAT1 TNEG/TMFP3 TNEG/TMFP2 TNEG/TMFP1 TICLK3 TICLK2 TICLK1
H4 L3 N3 H2 K4 N2 H1 K2 M2 H3 K1 N1 F4 J4 M3 G2 15 J3 16 L2 17 G1 18 J1 19 M1 20
14 13 12 11 10 9 8 7 6
P1 T1 Y1 P2 U1 V3 P3 T3 W2 R3 V1 W3 R2 U2 AA1 U4 W1 AB1 T4 V4 Y2
RCLK3 RCLK2 RCLK1 RPOS/RDAT3 RPOS/RDAT2 RPOS/RDAT1 RNEG/RLCV3 RNEG/RLCV2 RNEG/RLCV1 TCLK3 TCLK2 TCLK1 TPOS/TDAT3 TPOS/TDAT2 TPOS/TDAT1 TNEG/TMFP3 TNEG/TMFP2 TNEG/TMFP1 TICLK3 TICLK2 TICLK1
H4 L3 N3 H2 K4 N2 H1 K2 M2 H3 K1 N1 F4 J4 M3 G2 15 J3 16 L2 17 G1 18 J1 19 M1 20
RPOS/RDAT3 RPOS/RDAT2 RPOS/RDAT1 RNEG/RLCV3 RNEG/RLCV2 RNEG/RLCV1 TCLK3 TCLK2 TCLK1 TPOS/TDAT3 TPOS/TDAT2 TPOS/TDAT1 TNEG/TMFP3 TNEG/TMFP2 TNEG/TMFP1 TICLK3 TICLK2 TICLK1
RDATO3 RDATO2 RDATO1 RFPO/RMFPO3 RFPO/RMFPO2 RFPO/RMFPO1 ROVRHD3 ROVRHD2 ROVRHD1 TFPO/TMFPO/TGAPCLK3 TFPO/TMFPO/TGAPCLK2 TFPO/TMFPO/TGAPCLK1 TDATI3 TDATI2 TDATI1 TFPI/TMFPI3 TFPI/TMFPI2 TFPI/TMFPI1
G
8 7 6
G
F
F
5 4 3 2 1 0
W7 Y9 AA9 W9 Y10 AA10
RADEASTCK RADEASTFP RADEAST RADWESTCK RADWESTFP RADWEST CLK52M XCLK_T1 XCLK_E1 RECVCLK3 RECVCLK2 RECVCLK1 DS3-ALRM
AB10 E2 F3 G3 E4 F2
5 4 3
W7 Y9 AA9
RADEASTCK RADEASTFP RADEAST RADWESTCK RADWESTFP RADWEST CLK52M XCLK_T1 XCLK_E1 RECVCLK3 RECVCLK2 RECVCLK1 DS3-ALRM
AB10 E2 F3 G3 E4 F2
5 4 3 2 1 0
W7 Y9 AA9 W9 Y10 AA10
RADEASTCK RADEASTFP RADEAST RADWESTCK RADWESTFP RADWEST CLK52M XCLK_T1 XCLK_E1 RECVCLK3 RECVCLK2 RECVCLK1 DS3-ALRM
AB10 E2 F3 G3 E4 F2 47.0 R22
5 4 3 2 1 0
W7 Y9 AA9 W9 Y10 AA10
RADEASTCK RADEASTFP RADEAST RADWESTCK RADWESTFP RADWEST CLK52M XCLK_T1 XCLK_E1 RECVCLK3 RECVCLK2 RECVCLK1 DS3-ALRM
AB10 E2 F3 G3 E4 F2 47.0 R23
W9 2 1 Y10 0 AA10
E
E
47.0
47.0
R18
R19
15B4> 15H4> 15C4> 14C5<
DS3_CLK<11..0>\I XCLK_T1<3..0>\I XCLK_E1<3..0>\I
0 0 0 0
9 10 11
0 1 2
3 4 5
6 7 8
1 1 1
2 2 2
3 3 3
RECVCLK<3..0>\I
D
15D4>
DS3_REF<3..0>\I
T TP9 TMX1_RX2 T TP10 TMX1_RX3
1
T TP13 TMX2_RX2 T TP14 TMX2_RX3
2
T TP17 TMX3_RX2 T TP18 TMX3_RX3
TP21 T TMX4_RX2 TP22 T TMX4_RX3
D
3
9H10<
TEMUX_PULLDOWN1<20..0>
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
9H8<
TEMUX_PULLDOWN2<20..0>
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
9H6<
TEMUX_PULLDOWN3<20..0>
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
9H3<
TEMUX_PULLDOWN4<20..0>
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8
330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330
330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330
330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330
7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7
6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6
C
5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5
330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330
C
2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2
3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3
RN89 4 RN96 1 RN96 2 RN96 3 RN96 4 RN97 1 RN97 2 RN97 3 RN97 4 RN98 1 RN98 2 RN98 3 RN98 4 RN99 1 RN99 2 RN99 3 RN99 4 RN100 1 RN100 2 RN100 3 RN100 4
RN101 RN101 RN101 RN101 RN102 RN102 RN102 RN102 RN103 RN103 RN103 RN103 RN104 RN104 RN104 RN104 RN108 RN108 RN108 RN108 RN109
RN74 RN74 RN74 RN77 RN77 RN77 RN77 RN78 RN78 RN78 RN78 RN80 RN80 RN80 RN80 RN81 RN81 RN81 RN81 RN82 RN82
RN82 RN82 RN83 RN83 RN83 RN83 RN84 RN84 RN84 RN84 RN85 RN85 RN85 RN85 RN88 RN88 RN88 RN88 RN89 RN89 RN89
1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1
B DRAWING ABBREV=TEMUX84_BLOCK TITLE=TEMUX84_BLOCK LAST_MODIFIED=Mon May 28 11:42:34 2001
B
PMC-Sierra, Inc.
A DOCUMENT NUMBER: PMC-2001170 DOCUMENT ISSUE NUMBER: 1 TITLE: OC-12 LINE CARD TEMUX-84 DS3 ENGINEER: PMC-SIERRA INC (HS) 10 9 8 7 6 5 4 3 2 ISSUE DATE: 2001/03/15 REVISION NUMBER: 1 PAGE:9 1 OF 19 A
10
13G8< 13D4< 11H6> 11H10> 10H6> 13G8< 11H6> 11H10> 10H6> 13D4<
9 SBI DROP
8
7
13G8< 13D4< 13D4< 13D4< 13D4< 11H6> 11H6> 11H6>
6
11H10> 10H10> 11H10> 10H10> 11H10> 10H10>
5 SDV5\I SDPL\I SDDP\I SDDATA<7..0>\I AJUST_REQ\I SDC1FP\I SBI DROP
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
SDV5\I SDPL\I SDDP\I SDDATA<7..0>\I AJUST_REQ\I
13G8< 13G8< 13G8<
11H6> 11H10> 10H10>
H
11H10> 13G8< 13D4< 10H6> 11H6> 13G8< 10H6> 11H6>11H10> 13D4< 10H6> 13G10< 11H6> 11G10> 13D10< 14C9>
H
13G10< 13D10< 11H6> 11G10> 10H10> 14C9>
SDC1FP\I 3.3 V 3.3 V 4.7K
G TEMUX#1 TEMUX-84 PM8316 3 of 4 MVED21 MVED20 MVED19 MVED18 MVED17/SBIDET1 MVED16/SBIDET0 MVED15/SAV5 MVED14/SAPL MVED13/SADP MVED12/SADATA7 MVED11/SADATA6 MVED10/SADATA5 MVED9/SADATA4 MVED8/SADATA3 MVED7/SADATA2 MVED6/SADATA1 MVED5/SADATA0 MVED4/SAC1FP MVED3/S77 MVED2 MVED1 CASED21 CASED20 CASED19/EFBWDREQ3 CASED18/EFBWCLK3 CASED17/IFBWEN3 CASED16/IFBWDAT3 CASED15/IFBWCLK3 CASED14 CASED13 CASED12/EFBWDREQ2 CASED11/EFBWCLK2 CASED10/IFBWEN2 CASED9/IFBWDAT2 CASED8/IFBWCLK2 CASED7 CASED6 CASED5/EFBWDREQ1 CASED4/EFBWCLK1 CASED3/IFBWEN1 CASED2/IFBWDAT1 CASED1/IFBWCLK1 CCSED3 CCSED2 CCSED1 4.7K
PBGA U11
2
1 0 T22 R20 R22 D9 A9 B9 C9 D7 A8 B8 C8 A7 A6 D6 C7 B6 A5 C6 B5 A4 C5 A2 A3 B3 G22 G21 F22 G20 E19 F21 E22 C20 E21 E20 D21 C21 B22 D20 B21 A21 B20 B19 A20 A19 B18 B17 D18 C16
PBGA U10
2 1 0 T22 R20 R22 D9 A9 B9 C9 D7 A8 B8 C8 A7 A6 D6 C7 B6 A5 C6 B5 A4 C5 A2 A3 B3 G22 G21 F22 G20 E19 F21 E22 C20 E21 E20 D21 C21 B22 D20 B21 A21 B20 B19 A20 A19 B18 B17 D18 C16 D17
G
TEMUX#2 TEMUX-84 PM8316 3 of 4 MVED21 MVED20 MVED19 MVED18 MVED17/SBIDET1 MVED16/SBIDET0 MVED15/SAV5 MVED14/SAPL MVED13/SADP MVED12/SADATA7 MVED11/SADATA6 MVED10/SADATA5 MVED9/SADATA4 MVED8/SADATA3 MVED7/SADATA2 MVED6/SADATA1 MVED5/SADATA0 MVED4/SAC1FP MVED3/S77 MVED2 MVED1 CASED21 CASED20 CASED19/EFBWDREQ3 CASED18/EFBWCLK3 CASED17/IFBWEN3 CASED16/IFBWDAT3 CASED15/IFBWCLK3 CASED14 CASED13 CASED12/EFBWDREQ2 CASED11/EFBWCLK2 CASED10/IFBWEN2 CASED9/IFBWDAT2 CASED8/IFBWCLK2 CASED7 CASED6 CASED5/EFBWDREQ1 CASED4/EFBWCLK1 CASED3/IFBWEN1 CASED2/IFBWDAT1 CASED1/IFBWCLK1 CCSED3 CCSED2 CCSED1
A17 3 B16 4 C15 5 A16 6 B15 7 A15 8 C14 B14 A14 D14 C13 B13 D13 C12 B12 D12 A11 B11 D10 A10 9 B10 10 R19 P20 P21 P22 P19 N20 N22 N19 M20 M21 M22 L22 L20 K19 K22 K20 J19 J22 J21 J20 H19 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
F
7 6 5 4 3 2 1 0
RN154 RN147 RN147 RN53 RN53 RN57 RN57 RN57 RN152 RN152 RN152 RN149
22 22 22 22 22 22 22 22 22 22 22 22
MVID21 MVID20 MVID19 MVID18 MVID17 MVID16 MVID15 MVID14/SDV5 MVID13/SDPL MVID12/SDDP MVID11/SDDATA7 MVID10/SDDATA6 MVID9/SDDATA5 MVID8/SDDATA4 MVID7/SDDATA3 MVID6/SDDATA2 MVID5/SDDATA1 MVID4/SDDATA0 MVID3/SAJUST_REQ MVID2/SBIACT MVID1/SDC1FP CASID21 CASID20 CASID19 CASID18 CASID17 CASID16/EFBWDAT3 CASID15/EFBWEN3 CASID14 CASID13 CASID12 CASID11 CASID10 CASID9/EFBWDAT2 CASID8/EFBWEN2 CASID7 CASID6 CASID5 CASID4 CASID3 CASID2/EFBWDAT1 CASID1/EFBWEN1 CCSID3 CCSID2 CCSID1 TS0ID
RN146 RN146 RN146 RN146 RN146 RN146 RN184 RN184 RN184 RN184 RN184 RN184
0 0 0 0 0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
RN58 RN58 RN59 RN51 RN51 RN52 RN52 RN52 RN58 RN52 RN58 RN59
22 22 22 22 22 22 22 22 22 22 22 22
E
R19 11 P20 12 P21 13 P22 14 P19 15 N20 16 N22 17 N19 18 M20 19 M21 20 M22 21 L22 22 L20 23 K19 24 K22 25 K20 26 J19 27 J22 28 J21 29 J20 30 H19 31 H22 32 H21 33 H20 34
MVID21 MVID20 MVID19 MVID18 MVID17 MVID16 MVID15 MVID14/SDV5 MVID13/SDPL MVID12/SDDP MVID11/SDDATA7 MVID10/SDDATA6 MVID9/SDDATA5 MVID8/SDDATA4 MVID7/SDDATA3 MVID6/SDDATA2 MVID5/SDDATA1 MVID4/SDDATA0 MVID3/SAJUST_REQ MVID2/SBIACT MVID1/SDC1FP CASID21 CASID20 CASID19 CASID18 CASID17 CASID16/EFBWDAT3 CASID15/EFBWEN3 CASID14 CASID13 CASID12 CASID11 CASID10 CASID9/EFBWDAT2 CASID8/EFBWEN2 CASID7 CASID6 CASID5 CASID4 CASID3 CASID2/EFBWDAT1 CASID1/EFBWEN1 CCSID3 CCSID2 CCSID1 TS0ID
RN184 RN184 RN194 RN194 RN194 RN194 RN194 RN194 RN194 RN194 RN200 RN200
0 0 0 0 0 0 0 0 0 0 0 0
RN44
7 6 5 4 3 2 1 0
RN44
CMV8MCLK CMVFPC CMVFPB
A17 3 B16 4 C15 5 A16 6 B15 7 A15 8 C14 B14 A14 D14 C13 B13 D13 C12 B12 D12 A11 B11 D10 A10 9 B10 10
CMV8MCLK CMVFPC CMVFPB
F
E
H22 32 H21 33 H20 34
D
D17
H-MVIP H-MVIP H-MVIP_PULLDOWN2<34..0> H-MVIP_PULLDOWN1<34..0>
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
D
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330
7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5
RN109 RN109 RN109 RN110 RN110 RN110 RN110 RN111 RN111 RN111 RN111 RN112 RN112 RN112 RN112 RN113 RN113 RN113 RN113 RN116 RN116 RN116 RN116 RN117 RN117 RN117 RN117 RN118 RN118 RN118 RN118 RN124 RN124 RN124 RN124
RN125 RN125 RN125 RN125 RN126 RN126 RN126 RN126 RN127 RN127 RN127 RN127 RN128 RN128 RN128 RN128 RN129 RN129 RN129 RN129 RN130 RN130 RN130 RN130 RN131 RN131 RN131 RN131 RN137 RN137 RN137 RN137 RN138 RN138 RN138
C
2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4
1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3
8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6
330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330
C
SBI ADD
B
SBI ADD SAV5\I SAPL\I SADP\I SADATA<7..0>\I SAC1FP\I
13D10> 13D10> 13D10> 13D10> 13D10>
SAV5\I SAPL\I SADP\I SADATA<7..0>\I SAC1FP\I
B
13D10> 13D10> 13D10> 13D10> 13D10>
PMC-Sierra, Inc.
A DRAWING ABBREV=TEMUX84_BLOCK TITLE=TEMUX84_BLOCK LAST_MODIFIED=Mon May 28 11:42:38 2001 10 9 8 7 6 5 4 3 DOCUMENT NUMBER: PMC-2001170 DOCUMENT ISSUE NUMBER: 1 TITLE: OC-12 LINE CARD TEMUX-84 1 & 2 SBI ENGINEER: PMC-SIERRA (HS) 2 ISSUE DATE: 2001/03/15 REVISION NUMBER: 1 PAGE:10 1 OF 19 A
10 SBI DROP
10H6> 13D4< 10H6> 13D4< 13G8< 10H10> 11H6> 13G8< 10H10> 11H6> 13G8< 10H10> 11H6> 13G8< 10H10> 11H6>
9
8
7
6
13G8< 13D4< 11H10> 10H6> 10H10> 13G8< 13D4< 11H10> 10H6> 10H10> 13G8< 13D4< 11H10> 10H6> 10H10>
5 SDV5\I SDPL\I SDDP\I SDDATA<7..0>\I AJUST_REQ\I SDC1FP\I SBI DROP
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
SDV5\I SDPL\I
13G8< 13D4< 11H10> 10H6> 10H10> 13G10< 13D10< 11G10> 10H6> 10H10> 14C9>
H
10H6> 13D4<
H
SDDP\I
10H6> 13D4<
SDDATA<7..0>\I
13G10< 10H6> 10H10> 13D10< 11H6>
AJUST_REQ\I 3.3 V SDC1FP\I 3.3 V
14C9>
G
PBGA
U9 TEMUX#3 TEMUX-84 PM8316 3 of 4 MVED21 MVED20 MVED19 MVED18 MVED17/SBIDET1 MVED16/SBIDET0 MVED15/SAV5 MVED14/SAPL MVED13/SADP MVED12/SADATA7 MVED11/SADATA6 MVED10/SADATA5 MVED9/SADATA4 MVED8/SADATA3 MVED7/SADATA2 MVED6/SADATA1 MVED5/SADATA0 MVED4/SAC1FP MVED3/S77 MVED2 MVED1 CASED21 CASED20 CASED19/EFBWDREQ3 CASED18/EFBWCLK3 CASED17/IFBWEN3 CASED16/IFBWDAT3 CASED15/IFBWCLK3 CASED14 CASED13 CASED12/EFBWDREQ2 CASED11/EFBWCLK2 CASED10/IFBWEN2 CASED9/IFBWDAT2 CASED8/IFBWCLK2 CASED7 CASED6 CASED5/EFBWDREQ1 CASED4/EFBWCLK1 CASED3/IFBWEN1 CASED2/IFBWDAT1 CASED1/IFBWCLK1 CCSED3 CCSED2 CCSED1
4.7K
2 1 0
T22 R20 R22 D9 A9 B9 C9 D7 A8 B8 C8 A7 A6 D6 C7 B6 A5 C6 B5 A4 C5 A2 A3 B3 G22 G21 F22 G20 E19 F21 E22 C20 E21 E20 D21 C21 B22 D20 B21 A21 B20 B19 A20 A19 B18 B17 D18 C16
F
7 6 5 4 3 2 1 0
RN87 RN95 RN95 RN66 RN86 RN86 RN86 RN86 RN87 RN87 RN87 RN95
22 22 22 22 22 22 22 22 22 22 22 22
MVID21 MVID20 MVID19 MVID18 MVID17 MVID16 MVID15 MVID14/SDV5 MVID13/SDPL MVID12/SDDP MVID11/SDDATA7 MVID10/SDDATA6 MVID9/SDDATA5 MVID8/SDDATA4 MVID7/SDDATA3 MVID6/SDDATA2 MVID5/SDDATA1 MVID4/SDDATA0 MVID3/SAJUST_REQ MVID2/SBIACT MVID1/SDC1FP CASID21 CASID20 CASID19 CASID18 CASID17 CASID16/EFBWDAT3 CASID15/EFBWEN3 CASID14 CASID13 CASID12 CASID11 CASID10 CASID9/EFBWDAT2 CASID8/EFBWEN2 CASID7 CASID6 CASID5 CASID4 CASID3 CASID2/EFBWDAT1 CASID1/EFBWEN1 CCSID3 CCSID2 CCSID1 TS0ID
RN200 RN200 RN200 RN200 RN200 RN200 RN201 RN201 RN201 RN201 RN201 RN201
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0 0 0 0 0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
RN155 RN155 RN155 RN150 RN150 RN150 RN150 RN151 RN151 RN151 RN151 RN155
22 22 22 22 22 22 22 22 22 22 22 22
RN201 RN201 RN202 RN202 RN202 RN202 RN202 RN202 RN202 RN202 RN209 RN209
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
0 0 0 0 0 0 0 0 0 0 0 0
RN67
7 6 5 4 3 2 1 0
RN67
CMV8MCLK CMVFPC CMVFPB
A17 B16 C15 A16 B15 A15 C14 B14 A14 D14 C13 B13 D13 C12 B12 D12 A11 B11 D10 A10 B10 R19 P20 P21 P22 P19 N20 N22 N19 M20 M21 M22 L22 L20 K19 K22 K20 J19 J22 J21 J20 H19
3 4 5 6 7 8
2 1 0
T22 R20 R22 D9 A9 B9 C9 D7 A8 B8 C8 A7 A6 D6 C7 B6 A5 C6 B5 A4 C5 A2 A3 B3 G22 G21 F22 G20 E19 F21 E22 C20 E21 E20 D21 C21 B22 D20 B21 A21 B20 B19 A20 A19 B18 B17 D18 C16 D17
CMV8MCLK CMVFPC CMVFPB MVID21 MVID20 MVID19 MVID18 MVID17 MVID16 MVID15 MVID14/SDV5 MVID13/SDPL MVID12/SDDP MVID11/SDDATA7 MVID10/SDDATA6 MVID9/SDDATA5 MVID8/SDDATA4 MVID7/SDDATA3 MVID6/SDDATA2 MVID5/SDDATA1 MVID4/SDDATA0 MVID3/SAJUST_REQ MVID2/SBIACT MVID1/SDC1FP CASID21 CASID20 CASID19 CASID18 CASID17 CASID16/EFBWDAT3 CASID15/EFBWEN3 CASID14 CASID13 CASID12 CASID11 CASID10 CASID9/EFBWDAT2 CASID8/EFBWEN2 CASID7 CASID6 CASID5 CASID4 CASID3 CASID2/EFBWDAT1 CASID1/EFBWEN1 CCSID3 CCSID2 CCSID1 TS0ID H-MVIP
MVED21 MVED20 MVED19 MVED18 MVED17/SBIDET1 MVED16/SBIDET0 MVED15/SAV5 MVED14/SAPL MVED13/SADP MVED12/SADATA7 MVED11/SADATA6 MVED10/SADATA5 MVED9/SADATA4 MVED8/SADATA3 MVED7/SADATA2 MVED6/SADATA1 MVED5/SADATA0 MVED4/SAC1FP MVED3/S77 MVED2 MVED1 CASED21 CASED20 CASED19/EFBWDREQ3 CASED18/EFBWCLK3 CASED17/IFBWEN3 CASED16/IFBWDAT3 CASED15/IFBWCLK3 CASED14 CASED13 CASED12/EFBWDREQ2 CASED11/EFBWCLK2 CASED10/IFBWEN2 CASED9/IFBWDAT2 CASED8/IFBWCLK2 CASED7 CASED6 CASED5/EFBWDREQ1 CASED4/EFBWCLK1 CASED3/IFBWEN1 CASED2/IFBWDAT1 CASED1/IFBWCLK1 CCSED3 CCSED2 CCSED1
A17 B16 C15 A16 B15 A15 C14 B14 A14 D14 C13 B13 D13 C12 B12 D12 A11 B11 D10 A10 B10 R19 P20 P21 P22 P19 N20 N22 N19 M20 M21 M22 L22 L20 K19 K22 K20 J19 J22 J21 J20 H19 H22 H21 H20
3 4 5 6 7 8
4.7K
U8
PBGA
G TEMUX#4 TEMUX-84 PM8316 3 of 4
F
E
E
H22 32 H21 33 H20 34
D
D17
D
H-MVIP H-MVIP_PULLDOWN4<34..0> H-MVIP_PULLDOWN3<34..0>
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330
5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7
C RN138 4 RN157 1 RN157 2 RN157 3 RN157 4 RN160 1 RN160 2 RN160 3 RN160 4 RN161 1 RN161 2 RN161 3 RN161 4 RN179 1 RN179 2 RN179 3 RN179 4 RN265 1 RN265 2 RN265 3 RN265 4 RN266 1 RN266 2 RN266 3 RN266 4 RN267 1 RN267 2 RN267 3 RN267 4 RN268 1 RN268 2 RN268 3 RN268 4 RN269 1 RN269 2
RN182 1 RN180 1 RN181 1 RN185 1 RN183 1 RN186 1 RN187 1 RN188 1 RN178 1 RN177 1 RN175 1 RN172 1 RN171 1 RN165 1 RN170 1 RN164 1 RN162 1 RN269 3 RN269 4 RN270 1 RN270 2 RN270 3 RN270 4 RN271 1 RN271 2 RN271 3 RN271 4 RN272 1 RN272 2 RN272 3 RN272 4 RN273 1 RN273 2 RN273 3 RN273 4
8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5
330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330
C
SBI ADD SBI ADD B SAV5\I SAPL\I SADP\I SADATA<7..0>\I SAC1FP\I
13D10> 13D10> 13D10> 13D10> 13D10>
SAV5\I SAPL\I SADP\I SADATA<7..0>\I SAC1FP\I
B
13D10> 13D10> 13D10> 13D10> 13D10>
PMC-Sierra, Inc.
A DRAWING DOCUMENT NUMBER: PMC-2001170 DOCUMENT ISSUE NUMBER: 1 TITLE: OC-12 LINE CARD TEMUX-84 3 & 4 SBI ENGINEER: PMC-SIERRA INC (HS) 3 2 ISSUE DATE: 2001/03/15 REVISION NUMBER: 1 PAGE:11 1 OF 19 A
ABBREV=TEMUX84_BLOCK TITLE=TEMUX84_BLOCK LAST_MODIFIED=Mon May 28 11:42:42 2001 10 9 8 7 6 5 4
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H PBGA U11 3.3 V
A18 A22 AB17 D11 D16 D4 E1 F20 L1 L19 R21 R4 V2 W16 W4 W8 Y18 Y20 Y5 C2 D3 J2 R1 U3 AB2 AB9 Y12 Y15 AB19 N4 V20 U19 N21 K21 C22 C18 A13 B7
PBGA U10 TEMUX-84 PM8316 4 of 4 3.3 V VSS<69> VSS<68> VSS<67> VSS<66> VSS<65> VSS<64> VSS<63> VSS<62> VSS<61> VSS<60> VSS<59> VSS<58> VSS<57> VSS<66> VSS<55> VSS<54> VSS<53> VSS<52> VSS<51> VSS<50> VSS<49> VSS<48> VSS<47> VSS<46> VSS<45> VSS<44> VSS<43> VSS<42> VSS<41> VSS<40> VSS<39> VSS<38> VSS<37> VSS<36> VSS<35> VSS<34> VSS<33> VSS<32> VSS<31> VSS<30> VSS<29> VSS<28> VSS<27> VSS<26> VSS<25> VSS<24> VSS<23> VSS<22> VSS<21> VSS<20> VSS<19> VSS<18> VSS<17> VSS<16> VSS<15> VSS<14> VSS<13> VSS<12> VSS<11> VSS<10> VSS<9> VSS<8> VSS<7> VSS<6> VSS<5> VSS<4> VSS<3> VSS<2> VSS<1>
C4 A12 AA2 AA3 AA7 AB12 AB15 AB21 AB8 B4 C11 C17 C19 C3 D15 D19 D22 D5 D8 F1 G19 G4 J10 J11 J12 J13 J14 J9 K10 K11 K12 K13 K14 K3 K9 L10 L11 L12 L13 L14 L21 L9 M10 M11 M12 M13 M14 M19 M4 M9 N10 N11 N12 N13 N14 N9 P10 P11 P12 P13 P14 P9 T2 V21 V22 W21 Y11 Y14 Y17
PBGA U9 TEMUX-84 PM8316 4 of 4 3.3 V VSS<69> VSS<68> VSS<67> VSS<66> VSS<65> VSS<64> VSS<63> VSS<62> VSS<61> VSS<60> VSS<59> VSS<58> VSS<57> VSS<66> VSS<55> VSS<54> VSS<53> VSS<52> VSS<51> VSS<50> VSS<49> VSS<48> VSS<47> VSS<46> VSS<45> VSS<44> VSS<43> VSS<42> VSS<41> VSS<40> VSS<39> VSS<38> VSS<37> VSS<36> VSS<35> VSS<34> VSS<33> VSS<32> VSS<31> VSS<30> VSS<29> VSS<28> VSS<27> VSS<26> VSS<25> VSS<24> VSS<23> VSS<22> VSS<21> VSS<20> VSS<19> VSS<18> VSS<17> VSS<16> VSS<15> VSS<14> VSS<13> VSS<12> VSS<11> VSS<10> VSS<9> VSS<8> VSS<7> VSS<6> VSS<5> VSS<4> VSS<3> VSS<2> VSS<1>
C4 A12 AA2 AA3 AA7 AB12 AB15 AB21 AB8 B4 C11 C17 C19 C3 D15 D19 D22 D5 D8 F1 G19 G4 J10 J11 J12 J13 J14 J9 K10 K11 K12 K13 K14 K3 K9 L10 L11 L12 L13 L14 L21 L9 M10 M11 M12 M13 M14 M19 M4 M9 N10 N11 N12 N13 N14 N9 P10 P11 P12 P13 P14 P9 T2 V21 V22 W21 Y11 Y14 Y17 A18 A22 AB17 D11 D16 D4 E1 F20 L1 L19 R21 R4 V2 W16 W4 W8 Y18 Y20 Y5 C2 D3 J2 R1 U3 AB2 AB9 Y12 Y15 AB19 N4 V20 U19 N21 K21 C22 C18 A13 B7
PBGA U8 TEMUX-84 PM8316 4 of 4 3.3 V VSS<69> VSS<68> VSS<67> VSS<66> VSS<65> VSS<64> VSS<63> VSS<62> VSS<61> VSS<60> VSS<59> VSS<58> VSS<57> VSS<66> VSS<55> VSS<54> VSS<53> VSS<52> VSS<51> VSS<50> VSS<49> VSS<48> VSS<47> VSS<46> VSS<45> VSS<44> VSS<43> VSS<42> VSS<41> VSS<40> VSS<39> VSS<38> VSS<37> VSS<36> VSS<35> VSS<34> VSS<33> VSS<32> VSS<31> VSS<30> VSS<29> VSS<28> VSS<27> VSS<26> VSS<25> VSS<24> VSS<23> VSS<22> VSS<21> VSS<20> VSS<19> VSS<18> VSS<17> VSS<16> VSS<15> VSS<14> VSS<13> VSS<12> VSS<11> VSS<10> VSS<9> VSS<8> VSS<7> VSS<6> VSS<5> VSS<4> VSS<3> VSS<2> VSS<1>
C4 A12 AA2 AA3 AA7 AB12 AB15 AB21 AB8 B4 C11 C17 C19 C3 D15 D19 D22 D5 D8 F1 G19 G4 J10 J11 J12 J13 J14 J9 K10 K11 K12 K13 K14 K3 K9 L10 L11 L12 L13 L14 L21 L9 M10 M11 M12 M13 M14 M19 M4 M9 N10 N11 N12 N13 N14 N9 P10 P11 P12 P13 P14 P9 T2 V21 V22 W21 Y11 Y14 Y17 A18 A22 AB17 D11 D16 D4 E1 F20 L1 L19 R21 R4 V2 W16 W4 W8 Y18 Y20 Y5 C2 D3 J2 R1 U3 AB2 AB9 Y12 Y15 AB19 N4 V20 U19 N21 K21 C22 C18 A13 B7
H TEMUX-84 PM8316 4 of 4
G
1.8 V
VDD3_3<19> VDD3_3<18> VDD3_3<17> VDD3_3<16> VDD3_3<15> VDD3_3<14> VDD3_3<13> VDD3_3<12> VDD3_3<11> VDD3_3<10> VDD3_3<9> VDD3_3<8> VDD3_3<7> VDD3_3<6> VDD3_3<5> VDD3_3<4> VDD3_3<3> VDD3_3<2> VDD3_3<1> VDD1_8<19> VDD1_8<18> VDD1_8<17> VDD1_8<16> VDD1_8<15> VDD1_8<14> VDD1_8<13> VDD1_8<12> VDD1_8<11> VDD1_8<10> VDD1_8<9> VDD1_8<8> VDD1_8<7> VDD1_8<6> VDD1_8<5> VDD1_8<4> VDD1_8<3> VDD1_8<2> VDD1_8<1>
1.8 V
A18 A22 AB17 D11 D16 D4 E1 F20 L1 L19 R21 R4 V2 W16 W4 W8 Y18 Y20 Y5 C2 D3 J2 R1 U3 AB2 AB9 Y12 Y15 AB19 N4 V20 U19 N21 K21 C22 C18 A13 B7
VDD3_3<19> VDD3_3<18> VDD3_3<17> VDD3_3<16> VDD3_3<15> VDD3_3<14> VDD3_3<13> VDD3_3<12> VDD3_3<11> VDD3_3<10> VDD3_3<9> VDD3_3<8> VDD3_3<7> VDD3_3<6> VDD3_3<5> VDD3_3<4> VDD3_3<3> VDD3_3<2> VDD3_3<1> VDD1_8<19> VDD1_8<18> VDD1_8<17> VDD1_8<16> VDD1_8<15> VDD1_8<14> VDD1_8<13> VDD1_8<12> VDD1_8<11> VDD1_8<10> VDD1_8<9> VDD1_8<8> VDD1_8<7> VDD1_8<6> VDD1_8<5> VDD1_8<4> VDD1_8<3> VDD1_8<2> VDD1_8<1>
1.8 V
VDD3_3<19> VDD3_3<18> VDD3_3<17> VDD3_3<16> VDD3_3<15> VDD3_3<14> VDD3_3<13> VDD3_3<12> VDD3_3<11> VDD3_3<10> VDD3_3<9> VDD3_3<8> VDD3_3<7> VDD3_3<6> VDD3_3<5> VDD3_3<4> VDD3_3<3> VDD3_3<2> VDD3_3<1> VDD1_8<19> VDD1_8<18> VDD1_8<17> VDD1_8<16> VDD1_8<15> VDD1_8<14> VDD1_8<13> VDD1_8<12> VDD1_8<11> VDD1_8<10> VDD1_8<9> VDD1_8<8> VDD1_8<7> VDD1_8<6> VDD1_8<5> VDD1_8<4> VDD1_8<3> VDD1_8<2> VDD1_8<1>
1.8 V
VDD3_3<19> VDD3_3<18> VDD3_3<17> VDD3_3<16> VDD3_3<15> VDD3_3<14> VDD3_3<13> VDD3_3<12> VDD3_3<11> VDD3_3<10> VDD3_3<9> VDD3_3<8> VDD3_3<7> VDD3_3<6> VDD3_3<5> VDD3_3<4> VDD3_3<3> VDD3_3<2> VDD3_3<1> VDD1_8<19> VDD1_8<18> VDD1_8<17> VDD1_8<16> VDD1_8<15> VDD1_8<14> VDD1_8<13> VDD1_8<12> VDD1_8<11> VDD1_8<10> VDD1_8<9> VDD1_8<8> VDD1_8<7> VDD1_8<6> VDD1_8<5> VDD1_8<4> VDD1_8<3> VDD1_8<2> VDD1_8<1>
F
E
VSS<69> VSS<68> VSS<67> VSS<66> VSS<65> VSS<64> VSS<63> VSS<62> VSS<61> VSS<60> VSS<59> VSS<58> VSS<57> VSS<66> VSS<55> VSS<54> VSS<53> VSS<52> VSS<51> VSS<50> VSS<49> VSS<48> VSS<47> VSS<46> VSS<45> VSS<44> VSS<43> VSS<42> VSS<41> VSS<40> VSS<39> VSS<38> VSS<37> VSS<36> VSS<35> VSS<34> VSS<33> VSS<32> VSS<31> VSS<30> VSS<29> VSS<28> VSS<27> VSS<26> VSS<25> VSS<24> VSS<23> VSS<22> VSS<21> VSS<20> VSS<19> VSS<18> VSS<17> VSS<16> VSS<15> VSS<14> VSS<13> VSS<12> VSS<11> VSS<10> VSS<9> VSS<8> VSS<7> VSS<6> VSS<5> VSS<4> VSS<3> VSS<2> VSS<1>
C4 A12 AA2 AA3 AA7 AB12 AB15 AB21 AB8 B4 C11 C17 C19 C3 D15 D19 D22 D5 D8 F1 G19 G4 J10 J11 J12 J13 J14 J9 K10 K11 K12 K13 K14 K3 K9 L10 L11 L12 L13 L14 L21 L9 M10 M11 M12 M13 M14 M19 M4 M9 N10 N11 N12 N13 N14 N9 P10 P11 P12 P13 P14 P9 T2 V21 V22 W21 Y11 Y14 Y17
G
F
E
POWER D
POWER
POWER
POWER D
DECOUPLING FOR TEMUX-84 DEVICES. PLACE ONE CAP FOR EVERY TWO POWER PINS.
3.3 V
3.3 V
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
C218
C221
C224
C227
C230
C233
C236
C239
C242
0.1UF
C42
C46
C50
C54
C57
C59
C61
C31
C44
C
C48
C245
C
3.3 V
3.3 V
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
C34
C36
C78
C77
C76
C75
C74
C72
C71
C70
C52
C58
C60
C39
C64
C65
C66
C67
C68
0.1UF
C69
B
1.8 V
1.8 V
B
0.01UF
0.01UF
0.01UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
C219
C222
C225
C228
C231
C234
C237
C240
C243
0.01UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
C41
C45
C49
C53
C43
C47
C51
C55
C32
C33
C246
1.8 V
0.01UF 0.01UF
1.8 V
PMC-Sierra, Inc.
0.01UF 0.01UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF C223 C226 C229 C232 C235 C238 C241 C244 C247
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
C139
C217
C35
C37
C38
C40
C56
C62
C63
C73
C220
A
DOCUMENT NUMBER: PMC-2001170 DOCUMENT ISSUE NUMBER: 1 TITLE: OC12 DESIGN POWER ENGINEER: PMC-SIERRA INC. (HS)
ISSUE DATE: 00/12/05 REVISION NUMBER: 1 PAGE:12 1 OF 19
A
10
9
8
7
6
5
4
3
2
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION
3.3 V
C88 0.01UF R78 1UF C297 0.01UF 0.1UF
DATE
APPR
SBI BUS MICTOR CONNECTOR
H
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37
3.3 V
0 R58
J3
2-767004-2
SCL DSA B-CLK B-D15 B-D14 B-D13 B-D12 B-D11 B-D10 B-D9 B-D8 B-D7 B-D6 B-D5 B-D4 B-D3 B-D2 B-D1 B-D0
AVDH0
C280
13F1<
3.3
AVDH1
C301
13F1<
H
MICTOR 38 PIN
+5V GND_D A-CLK A-D15 A-D14 A-D13 A-D12 A-D11 A-D10 A-D9 A-D8 A-D7 A-D6 A-D5 A-D4 A-D3 A-D2 A-D1 A-D0
C89 0.01UF
11G10> 10H10> 10H6> 11H6>
AJUST_REQ\I
G
13D10>
SADATA<7..0>\I
0.1UF
SDDATA<7..0>\I
10H10>10H6> 11H10>11H6>
R61
C90 0.01UF
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
LVDS LINKS
RC1FP\I 50 50 50 50 OHM OHM OHM OHM
14C9> 18D10> 18D10> 18F10> 18G10>
1.8 V
0
C302
R79
0.1UF
C281
R59
C298 0.01UF
0.1UF
15E4> 14C9> 13D10> 13D10> 13D10>
SREFCLK<4>\I RC1FP\I SAPL\I SADP\I SAV5\I
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38
3.3 V SAC1FP\I SDPL\I SDDP\I SDV5\I
13D10> 10H10>10H6> 11H10> 11H6> 10H10>10H6> 11H10> 11H6> 10H10>10H6> 11H10> 11H6>
0
3.3 V CSU_AVDH
13G1<
0
AVDH2
13F1<
G
C282
39 40 41 42 43
U15 SBS_LITE PM8611 3_OF_3
RX RPWRK\I
RNWRK\I RPPROT\I RNPROT\I
1.8 V
.47 C91 0.01UF R62 4.7UF C283 G4 H4 J3 J4
+
AVDL[3] AVDL[2] AVDL[1] AVDL[0] DVDDI[7] DVDDI[6] DVDDI[5] DVDDI[4] DVDDI[3] DVDDI[2] DVDDI[1] DVDDI[0] DVDDO[13] DVDDO[12] DVDDO[11] DVDDO[10] DVDDO[9] DVDDO[8] DVDDO[7] DVDDO[6] DVDDO[5] DVDDO[4] DVDDO[3] DVDDO[2] DVDDO[1] DVDDO[0] DVDDQ[2] DVDDQ[1] DVDDQ[0] AVDQ GND[3] GND[2] GND[1] GND[0]
CSU_AVDH AVDH[2] AVDH[1] AVDH[0] VSS[34] VSS[33] VSS[32] VSS[31] VSS[30] VSS[29] VSS[28] VSS[27] VSS[26] VSS[25] VSS[24] VSS[23] VSS[22] VSS[21] VSS[20] VSS[19] VSS[18] VSS[17] VSS[16] VSS[15] VSS[14] VSS[13] VSS[12] VSS[11] VSS[10] VSS[9] VSS[8] VSS[7] VSS[6] VSS[5] VSS[4] VSS[3] VSS[2] VSS[1] VSS[0]
H1 C1 D4 E3
CSU_AVDH AVDH2 AVDH1 AVDH0
13H3> 13G1> 13H1> 13H3>
F 3.3 V
50 50 50 50
OHM OHM OHM OHM
TX TPWRK\I
TNWRK\I TPPROT\I TNPROT\I TC1FP\I
1.8 V
18C10< 18C10< 18F10< 18F10< 14D9< 15B3<
1.8 V
.47 C93 0.01UF 4.7UF R73 C284
K2 L1 P5 P9 L13 G13 A11 A5 N1 N2 M4 P7 N9 P13 H14 E13 A13 A9 C8 C6 A3 A2 P8 J13 C10
3.3 V
10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K
U15 SBS_LITE PM8611 1_OF_3
F2 F1 G2 G1 N4
10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K
8 7 6 5 8 7 6 5 8 7 6 5
8 7 6 5 8 7 6 5 8 7 6
1.8 V
.47 R74 C94 0.01UF 4.7UF C285
RN233 RN233 RN233 RN233 RN234 RN234 RN234 RN234 RN235 RN235 RN235 RN235
E
RN236 RN236 RN236 RN236 RN237 RN237 RN237 RN237 RN238 RN238 RN238
RPWRK RNWRK RPPROT RNPROT RC1FP ODATA[7] ODATA[6] ODATA[5] ODATA[4] ODATA[3] ODATA[2] ODATA[1] ODATA[0] ODP OPL OV5 OTPL OTAIS OC1FP JUST_REQ
TPWRK TNWRK TPPROT TNPROT TC1FP IDATA[7] IDATA[6] IDATA[5] IDATA[4] IDATA[3] IDATA[2] IDATA[1] IDATA[0] IDP IPL IV5 ITPL ITAIS IC1FP
E2 E1 D1 D2 C3 E11 D14 D12 D13 C14 C12 C13 B14 E14 F14 F13 F11 G11 F12
1 2 3 4 1 2 3 4 1 2 3 4
1 2 3 4 1 2 3 4 1 2 3
+
+
3.3 V
7 6 5 4 3 2 1 0
RN60 RN163 RN176 RN176 RN90 RN90 RN90 RN90 RN91 RN91 RN91 RN95 RN91
1 2 3 4 1 2 3 4 1 2 3 4 4
8 7 6 5 8 7 6 5 8 7 6 5 5
22 22 22 22 22 22 22 22 22 22 22 22 22
C7 B7 D7 A6 D6 B5 D5 A4 C4 D9 B8 A8 D8 C9 K12
RN209 RN209 RN209 RN209 RN209 RN209 RN210 RN210 RN210 RN210 RN210
3 4 5 6 7 8 1 2 3 4 5
14 13 12 11 10 9 16 15 14 13 12
0 0 0 0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
3.3 V
0 0.1UF R77 C95 0.01UF C286
H3 G7 G8 H7 H8
SDDATA<7..0>\I SDDP\I SDPL\I SDV5\I IC1FP\I
13G10< 11B6< 13G10< 11B6< 13H10< 11B6< 13G10< 11B6<
11B1< 11B1< 11B1< 11B1<
10B6< 10B6< 10B6< 10B6<
10B1< 10B1< 10B1< 10B1<
SADATA<7..0>\I SADP\I SAPL\I SAV5\I SAC1FP\I AJUST_REQ\I
10H10> 10H6> 11H10> 11H6> 10H10> 10H6> 11H10> 11H6> 11H6> 10H10> 10H6> 11H10> 10H10> 10H6> 11H10> 11H6> 14C9>
B1 D3 E4 G3 H2 J1 J2 K1 K3 K4 L3 P2 P4 M5 L7 M7 L8 M9 N12 L12 K11 H11 G14 E12 B13 B11 C11 A10 D10 B9 A7 B6 C5 B4 B3
F
E
POWER
13H8< 11B1< 11A6< 10B1< 10A6< 11H6> 11G10>10H6> 10H10>
D
SBI336 ADD BUS
BUS_DATA_INT
SBI336 DROP BUS
1.8 V
D
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
10UF
C289
C299
C303
C305
0.1UF
10UF
C96
C85
C86
C87
U15 C
14E10<> 3B6<>
PLACE ONE CAP FOR EVERY SBS_LITE PM8611 2_OF_3 3.3 V ADDR_A<8..0>\I
N11 P12 M12 N13 N14 M13 M14 L14 L11 J12 H13 J11 J14 H12 C2 B2 F3 F4 A12 B12 B10 L5 R83 3.16K 8 7 6 5 4 3 2 1 0
DVDDI PINS.
C92
MICROPROCESSOR / JTAG INTERFACE
C307
+
+
C
DATA_A<15..0>\I
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
14F10>
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
3.3 V
4.7K
R55
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
C288
C291
C292
C294
C295
C296
C300
C304
C306
B
14G9> 14G9> 14G9> 14G9< 14F9> 14F9> 18G10>
SBS_CSB\I RDB\I WRB\I SBS_INTB\I RSTB\I OCMP\I RWSEL\I
L2 M2 M1 M3 G12 P3 D11 K14 N3
C308
ALE CSB RDB WRB INTB RSTB OCMP OUSER2 RWSEL
RES RESK ATB1 ATB0 SYSCLK SREFCLK ICMP IUSER2
0.1UF
22 1 22 3 22 4 22 1 22 2 22 3 22 4 22 1 22 2 22 3 22 4 22 1 22 2 22 3 22 4 22 1
8 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8
RN166 RN163 RN163 RN163 RN166 RN166 RN166 RN167 RN167 RN167 RN167 RN168 RN168 RN168 RN168 RN169
L4 N5 N6 P6 M6 L6 N7 M8 N8 L9 P10 M10 N10 L10 P11 M11
D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
A[8]/TRS A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0] TRSTB TCK TMS TDI TDO
C100
C101
C102
10UF
10UF
C287
C290
10UF
C293
TRSTB\I TCK\I TMS\I TDO_TEMUX4\I TDO_SBS\I
17C3> 14A5> 14A5> 8H10> 16C7< 19F2<
C103
C97
C98
C99
+
+
+
B
SREFCLK<4>\I ICMP\I
15E4> 14F9>
PLACE ONE CAP FOR EVERY DVDDO PINS.
MICRO_INT_JTAG
PMC-Sierra, Inc.
A DRAWING ABBREV=SBS_BLOCK TITLE=SBS_BLOCK LAST_MODIFIED=Mon May 28 11:42:52 2001 DOCUMENT NUMBER: PMC-2001170 DOCUMENT ISSUE NUMBER: 1 TITLE: OC-12 LINE CARD SBS-LITE SECTION ENGINEER: PMC-SIERRA INC (HS) 10 9 8 7 6 5 4 3 2 ISSUE DATE: 2001/03/15 REVISION NUMBER: 1 PAGE:13 1 OF 19 A
10
9 3.3 V
8
7
6 NOTE: (DEPENDS ON POSITION OF CONNECTOR)
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION
3.3 V H
H
8 6 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 5
RN227 RN37 RN199 RN199 RN199 RN232 RN232 RN232 RN232 RN239 RN239 RN239 RN239 RN248 RN248 RN248 RN248 RN199 RN37
1 3 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 4
4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K
LCLK IS CHOSEN FROM EITHER LCKLN\I OR LCLK_P\I OUTPUT_INTB ROUTES TO EITHER OUTPUT_INTBN\I OR OUTPUT_INTB_P\I CPLD_CSB IS CHOSEN FROM EITHER CPLD_CSB_P\I OR CSB_0N\I OUTPUT_INTB SHOULD BE INVERTED BY CPLD BEFORE GOING TO LED
DATE
APPR
U17 U15 U10 U6 U4 R17 R4 L17 K4 F17 F4 D17 D15 D11 D6 D4
G4 B3 C7 A10 B14 B17 E17 F20 M19 T20 W18 U13 V10 Y9 W5 P2 F1
PBGA U26
G20 H17 H18 H19 H20 J17 J18 J19 J20 K17 K18 K19 C18 D18 C20 D19 E18 D20 E19 F18 G17 E20 F19 G19 C14 A15 B15 D14 C15 A16 C16 A17 A18 D16 C17 B18 D10 C10 B10 C11 B11 A12 C12 D12 A13 B13 C13 A14 A5 B6 B7 A7 D8 C8 B8 A8 D9 C9 B9 A9 C3 B2 C4 D5 A3 B4 C5 A4 B5 C6 D7 G3 F2 F3 E2 E3 D1 E4 D2
DATA_P<15..0>\I
IO15<12> IO15<11> IO15<10> IO15<9> IO15<8> IO15<7> IO15<6> IO15<5> IO15<4> IO15<3> IO15<2> IO15<1> IO13<12> IO13<11> IO13<10> IO13<9> IO13<8> IO13<7> IO13<6> IO13<5> IO13<4> IO13<3> IO13<2> IO13<1> IO11<12> IO11<11> IO11<10> IO11<9> IO11<8> IO11<7> IO11<6> IO11<5> IO11<4> IO11<3> IO11<2> IO11<1>
L20 L18 L19 M20 M18 M17 N20 N19 N18 N17 P20 P19 P18 R20 P17 R18 T19 T18 U20 V20 T17 U19 V19 Y20 W19 V18 Y19 V17 Y18 V16 Y17 U14 Y16 W15 V14 Y15 W14 V13 W13 Y13 U12 V12 W12 Y12 U11 V11 W11 Y11 W9 V9 U9 Y8 W8 V8 Y7 W7 U8 V7 Y6 W6 U7 V6 V5 Y4 Y3 U5 V4 Y2 V3 V2 U3 T4 V1 T3 U1 R3 P4 R2 P3 R1 P1 N4 N3 N2 N1 M4 M3 M2 M1 L4 L3 L2 L1 C1 E1 C2 D3
16E1<>
PBGA
3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V
VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO
G
M12 M11 M10 M9 L12 L11 L10 L9 K12 K11 K10 K9 J12 J11 J10 J9 A6 A11 D13 B16 G18 K20 R19 U18 V15 Y14 Y10 W10 Y5 T1 K3 B1
13B10< 8A10< 13C5< 3B10<
7A10<
6A9<
15C3< 8B10< 7B10< 6B9< 5B9< 3C5< 15B3< 13B5< 15B1< 13B10< 5A9< 3A6< 15C1< 15B3< 15B3<
13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPARE2 TEMUX_CSB<3>\I TEMUX_CSB<2>\I TEMUX_CSB<1>\I TEMUX_CSB<0>\I DFP\I ICMP\I OCMP\I RSTB\I SPARE3 SPARE4 22 1 22 4 22 4 22 2 22 3 22 4 22 4 22 1 22 2 22 2 22 3 22 4 22 1 22 2 LOC_77M EXT_77M EXT_FP 77M_CLOCK
8 RN208 5 RN220 5 RN222 7 RN174 6 RN174 5 RN174 5 RN94 8 RN176 7 RN176 7 RN195 6 RN195 5 RN195 8 RN42 7 RN42
ADDR_A<13..0>\I
IO14<12> IO14<11> IO14<10> IO14<9> IO14<8> IO14<7> IO14<6> IO14<5> IO14<4> IO14<3> IO14<2> IO14<1> IO12<12> IO12<11> IO12<10> IO12<9> IO12<8> IO12<7> IO12<6> IO12<5> IO12<4> IO12<3> IO12<2> IO12<1>
0 0 0 0
2 3 4 5
15 14 13 12
RN122 RN122 RN122 RN122
3 2 1 0 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDR_P<17..0>\I
16G1>
DECOUPLING FOR XC95288XL. PLACE ONE CAP FOR EACH VCC PIN. 3.3 V F
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
F
C168
C190
C194
C198
C202
C206
WRB_P\I RDB_P\I RSTB_IN\I SBS_CSB_P\I SPECTRA_CSB_P\I OUTPUT_INTB_P\I TEMUX_IN_CSB_P\I CPLD_CSB_P\I READYB_P\I LCLK_P\I TRSTB_IN\I 06 11 RN122 07 10 RN122 9 RN122 08 0 0 0 0 0 0 0 0 0 0 0 0
1 2 3 4 5 6 7 8 1 2 3 4 16 15 14 13 12 11 10 9 16 15 14 13
16C1> 16C1> 17D3> 16D1> 16D1> 16C1< 16D1> 16D1> 16C1< 16C1> 14A5> 17C5<
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
C169
C191
C195
C199
C203
C207
0.1UF
3B6<> 13C10<>
DATA_A<15..0>\I
15F8> 14A9> 14A9> 15E10<
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 12 11 10 9 8 7 6 5 4 3 2 1 0
E
47 2 22 4 22 2 22 3 22 4 22 1 22 2 22 3 22 4 22 1 22 2 22 3 22 4 22 1 22 2 22 3 22 4 22 1 22 1 22 2 22 2 22 3 22 4 22 1 22 2 22 3 22 4 22 1 22 2 22 3
7 RN226 5 RN136 7 RN208 6 RN208 5 RN208 8 RN215 7 RN215 6 RN215 5 RN215 8 RN216 7 RN216 6 RN216 5 RN216 8 RN217 7 RN217 6 RN217 5 RN217 8 RN218 8 RN41 7 RN41 7 RN218 6 RN218 5 RN218 8 RN219 7 RN219 6 RN219 5 RN219 8 RN220 7 RN220 6 RN220 8 RN221 7 RN221 6 RN221 5 RN221 8 RN222 7 RN222 6 RN222 6 RN41
IO10<12> IO9<12> IO10<11> IO9<11> IO10<10> IO9<10> IO10<9> IO9<9> IO10<8> IO9<8> IO10<7> IO9<7> IO10<6> XC95288XL IO9<6> IO10<5> IO9<5> CPLD IO10<4> IO9<4> 1 OF 2 IO10<3> IO9<3> IO10<2> 288 MICROCELLS IO9<2> IO10<1> IO9<1> IO8<12> IO8<11> IO8<10> IO8<9> IO8<8> IO8<7> IO8<6> IO8<5> IO8<4> IO8<3> IO8<2> IO8<1> IO6<11> IO6<10> IO6<9> IO6<8> IO6<7> IO6<6> IO6<5> IO6<4> IO6<3> IO6<2> IO6<1> IO4<8> IO4<7> IO4<6> IO4<5> IO4<4> IO4<3> IO4<2> IO4<1> IO7<12> IO7<11> IO7<10> IO7<9> IO7<8> IO7<7> IO7<6> IO7<5> IO7<4> IO7<3> IO7<2> IO7<1> IO5<11> IO5<10> IO5<9> IO5<8> IO5<7> IO5<6> IO5<5> IO5<4> IO5<3> IO5<2> IO5<1> IO3<10> IO3<9> IO3<8> IO3<7> IO3<6> IO3<5> IO3<4> IO3<3> IO3<2> IO3<1> IO1<12> IO1<11> IO1<10> IO1<9> IO1<8> IO1<7> IO1<6> IO1<5> IO1<4> IO1<3> IO1<2> IO1<1> IO/GTS<1> IO/GTS<2> IO/GTS<3> IO/GTS<4>
U16 W16 B12 W17
3.3 V
DATAN<15..0>\I
19E5<>
C211
C210
C19 B20 B19 A20 A19 A1
13B10< 8B10< 13B10< 8A10<
7B10< 7A10<
6B9< 6A9<
5B9< 5A9<
3A6> 13B10> 8B10> 7B10> 6B9> 5B9> 3F6< 3A6< 13B10< 3A6< 3A6< 15C3<
SPECTRA_INTB\I SBS_INTB\I TEMUX_INTB<3>\I TEMUX_INTB<2>\I TEMUX_INTB<1>\I TEMUX_INTB<0>\I OUTPUT_INTB\I SPECTRA_CSB\I SBS_CSB\I RDB\I WRB\I SPARE1
IO16<12> IO16<11> IO16<10> IO16<9> IO16<8> IO16<7> IO16<6> IO16<5> IO16<4> IO16<3> IO16<2> IO16<1>
0 0 0 0 0 0 0 0 0 0 0 0
6 7 8 1 2 3 4 5 6 7 8 1
11 10 9 16 15 14 13 12 11 10 9 16
RN210 RN210 RN210 RN121 RN121 RN121 RN121 RN121 RN121 RN121 RN121 RN122
15 14 13 12 11 10 9 8 7 6 5 4
XC95288XL
CPLD - 288 MICROCELLS
2 OF 2 NC NC NC NC NC NC
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
NC NC NC NC NC
Y1 W20 W3 W2 W1
G
U26
E 3.3 V
6B9< 5B9< 8B10< 7B10<
ADDR_B<12..0>\I
RN123 RN123 RN123 RN123 RN123 RN123 RN123 RN123 RN132 RN132 RN132 RN132
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
C174
C192
C196
C200
C204
C208
0.1UF
ADDRN<17..0>\I
19F5>
3.3 V D
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF C175 C193 C197 C201 C205 C209 0.1UF C213
D
13F4> 6B9<> 5B9<> 8B10<> 7B10<>
TC1FP\I 22 1 22 2 22 3 22 4 22 1 22 2 22 3 22 3 FPOUT\I IC1FP\I SDC1FP\I RC1FP\I
DATA_B<7..0>\I
4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K
0.1UF
0.1UF
0.1UF
0.1UF
C170
C162
C164
C165
0.1UF
2 KHZ C
15C1< 5G9< 4D1< 7G10< 6G9< 8G10< 6G3< 5G2< 4D3< 8G2< 7G3< 11H6< 18B10< 15B3< 15B1< 13D4< 11G10< 10H6< 10G10< 15B3< 13H10< 13G4<
3 2 1 0 3 2 1 0
WRBN\I RDBN\I OUTPUT_INTBN\I CSB_0N\I CSB_1N\I READYBN\I LCLKN\I RECVCLK<0>\I RECVCLK<1>\I RECVCLK<2>\I RECVCLK<3>\I BP_FP_JUMPER CLOCK1_JUMPER CLOCK2_JUMPER FP1_JUMPER FP2_JUMPER CMP_JUMPER JUMPER_SIGNAL
CTCLK<3..0>\I 8 KHZ
RN134 5 RN36 7 RN196 6 RN196 5 RN134 8 RN134 7 RN134 6
LAC1<3..0>\I
47 47 47 47 47 47 47 47 47 47 47 47
2 3 4 2 3 4 1 2 3 4 1 2
7 RN73 6 RN73 5 RN73 7 RN212 6 RN75 5 RN75 8 RN76 7 RN76 6 RN76 5 RN76 8 RN133 7 RN133
K1 K2 J1 J2 J3 J4 H1 H2 H3 H4 G1 G2 T2 U2 W4 A2
IO2<12> IO2<11> IO2<10> IO2<9> IO2<8> IO2<7> IO2<6> IO2<5> IO2<4> IO2<3> IO2<2> IO2<1> IO/GCK<1> IO/GCK<2> IO/GCK<3> IO/GSR
19D5> 19D5> 19D5< 19D5> 19D5> 19D5< 19F5> 9D10> 9D10> 9D10> 9D10>
4 2 3 4 1 2 3
C166
7 6 5 4 3 2 1 0
3.3 V
C212
3.3 V
C
18E10> 18C10> 18G10>
BP_77M\I BP_FP\I BP_CMP\I
NOTE: SEE THE REF DESIGN FOR FURTHER DETAILS REGARDING THE CONNECTION OF THE PINS ON THE HEADER
HEADER 8X2
J10
1 3 5 7 9 11 13 15
3.3 V
2 4 6 8 10 12 14 16
B
B DRAWING
J15 1441P VERTICAL
3
CPLD ISP PORT
100MIL J12 +3_3V TRSTB TMS TDO_CPLD TDI TCK GND GND
1 2 3 4 5 6 7 8
ABBREV=CPLD TITLE=CPLD LAST_MODIFIED=Mon May 28 11:42:59 2001
5
2
SMB
4 1 2
47.0
EXT_77M
3.3 V 100MIL J13 +3_3V TRSTB TMS TDO TDI TCK GND GND
1 2 3 4 5 6 7 8
14E9< 15B3<
J11 R71 1442P VERTICAL
JTAG DEBUG PORT
TRSTB_IN\I TMS\I TDO_HDR\I TDO_PROC\I TCK\I
14E5> 17C5< 3A10< 5H9< 6H9< 3A10< 16C7> 19F2> 3A10< 5H9< 6H9< 7H10< 8G10< 13B5< 16C7< 19F2< 7G10< 8G10< 13B5< 16C7< 19F2<
PMC-Sierra, Inc.
DOCUMENT NUMBER: PMC-2001170 DOCUMENT ISSUE NUMBER: 1 TITLE: OC-12 LINE CARD CPLD ENGINEER: PMC-SEIRRA (HS) ISSUE DATE: 2001/03/15 REVISION NUMBER: 1 PAGE:14 1 OF 19 A
A
5
3
4
1
SMB
47.0 R72
EXT_FP
14E9< 15B3<
10
9
8
7
6
5
4
3
2
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE
3.3 V H 3.3 V
4.7K R93
REV
DESCRIPTION
DATE
APPR
H U20 SPEED GRADE C QSOP20
20 1
T1 CLOCK REFERENCE VCCA
T1 AND TELECOM CLOCKS
XCLK_T1<3..0>\I 37.056 MHZ
9D10<
Y2
0.1UF C137 4 2
32PPM OSC_EH26 3.3V VCC OUTPUT GND TRI_STATE 37.056MHZ
9 3 1 3
VCCB
OEA INA OEB INB
RN266 47
10
OA4 OA3 OA2 OA1 OA0 OB4 OB3 OB2 OB1 OB0
7 6 4 3 2 14 15 17 18 19 13
RN107 RN107 RN107 RN107
1 2 3 4
8 7 6 5
47 47 47 47
3 2 1 0
PI49FCT3805
12 11
GNDA GNDB GNDQ
R604
330
330
R609
G
TP20 T XCLK_T1
DECOUPLING FOR PI49FCT3805 DEVICES. PLACE ONE OF EACH TYPE OF CAP PER CHIP. G 3.3 V 3.3 V
MON
5 16 8
0.01UF
0.01UF
0.01UF
0.01UF
0.1UF
0.1UF
0.1UF
0.1UF
C171
C172
C173
C176
0.1UF
3.3 V SPEED GRADE C QSOP20
20
0.01UF
C129
C131
C133
C135
U14 3.3 V 77M CLOCK REFERENCE
4.7K R95 9
1
SBI AND TELECOM CLOCKS
LREFCLK<3..0>\I
2 3 4 1 3 4 1 7 6 5 8 6 5 8
VCCA
VCCB
OEA INA
LOC_77M
14E9<
10
F
0.1UF C141 4 2
Y6
20PPM OSC_EH26 3.3V VCC OUTPUT GND TRI_STATE 77.760MHZ
OA4 OA3 OA2 OA1 OA0 OB4 OB3 OB2 OB1 OB0
7 6 4 3 2 14 15 17 18 19 13
RN143 RN143 RN143 RN226 RN135 RN135 RN143
47 47 47 47 47 47 47
5G9<
6G9<
7G10< 8G10<
3 2 1 0 1 0
77.76 MHZ F TEL_CLK<1..0>\I 77.76 MHZ BP_77MOUT\I 77.76 MHZ
3F1< 4D1< 4D3< 18E10<
PI49FCT3805
12 3 1 1
RN268 47 U23
OEB INB GNDA GNDB GNDQ
3.3 V SPEED GRADE C QSOP20
20
11
1
MON
VCCA
VCCB
9
OEA INA
14E9>
77M_CLOCK TP26 T 77M_CLK
10
OA4 OA3 OA2 OA1 OA0 OB4 OB3 OB2 OB1 OB0
7 6 4 RN212 6 8 3 RN75 6 RN133 2 14 15 17 18 19
3 47 1 47 3 47
5 16 8
PI49FCT3805
E
12 11
OEB INB GNDA GNDB GNDQ
RN212 RN213 RN213 RN213 RN213
R67 R69
4 1 2 3 4
5 8 7 6 5
47 47 47 47 47
4 3 2 1 0
SREFCLK<4..0>\I 77.76 MHZ
1B8
5G2< 6G3< 7G3< 8G2< 13B5< 13H10<
C104
C177
E
R605
330
330
R610
MON
13
5 16 8
330
3.3 V DS3 CLOCK REFERENCE
4.7K R96
3.3 V
20
0.1UF
U24
3 1 4 9
C163
VCCA
1
D
4 2
Y4
VCCB
50PPM OSC_EP26 3.3V VCC OUTPUT GND TS/PD
TP27 T DS3_REF
330
SPEED GRADE C QSOP20
DS3 CLOCK REFERENCE
D DS3_REF<3..0>\I 51.84 MHZ
3 2 1 0 3 2 1 0
9D10<
OEA INA
51.84MHZ
RN265 47
10
OA4 OA3 OA2 OA1 OA0 OB4 OB3 OB2 OB1 OB0
7 6 4 3 2 14 15 17 18 19 13
RN105 1 RN105 2 RN105 3 RN105 4 RN106 1 RN106 2 RN106 3 RN106 4
8 7 6 5 8 7 6 5
47 47 47 47 47 47 47 47
PI49FCT3805
3.3 V E1 CLOCK REFERENCE
4.7K R97
12 1
OEB INB GNDA GNDB GNDQ
RN738 47
R606 330 330 R611
XCLK_E1<3..0>\I 49.152 MHZ
9D10<
11
0.1UF
Y3
C167 4 2
C
32PPM OSC_EH26 3.3V VCC OUTPUT GND TRI_STATE 49.152MHZ
MON
3 1 5 16 8
C
TP29 T XCLK_E1
1
3.3 V SPEED GRADE C QSOP20 J9
U13
DS3 MAPPING REFERENCE
DS3_CLK<11..0>\I
9E10<
VCCA
3.3 V
9 10
VCCB
14G9> 14G9> 14F9> 14F9> 13F4> 18C10> 18E10> 14A9> 18G10> 14C9> 14A9> 14F9> 14C9>
SPARE1 SPARE2 SPARE3 SPARE4 TC1FP\I BP_FP\I BP_77M\I EXT_77M BP_CMP\I FPOUT\I EXT_FP ICMP\I RC1FP\I
OEA INA OEB INB
B
U1
SPEED GRADE C QSOP20
20
OA4 OA3 OA2 OA1 OA0 OB4 OB3 OB2 OB1 OB0
7 6 4 3 2
44.736 MHZ RN214 RN214
1 2 3 4 1 2 3 8 7 6 5 8 7 6
47 47 47 47 47 47 47
0 1 2 3 4 5 6
1
PI49FCT3805
12 11
VCCA
GNDA GNDB GNDQ
3.3 V DS3 MAPPING REFERENCE
4.7K R271 2
9
VCCB
OEA INA
RN267 47
10
5
16
PI49FCT3805
8
OA4 OA3 OA2 OA1 OA0 OB4 OB3 OB2 OB1 OB0
7 6 4 RN133 5 RN135 8 3 RN135 2 7 14 15 17 18 19
14 RN214 15 RN214 17 RN223 18 RN223 19 RN223 13
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31
P_1 P_3 P_5 P_7 P_9 P_11 P_13 P_15 P_17 P_19 P_21 P_23 P_25 P_27 P_29 P_31
P_2 P_4 P_6 P_8 P_10 P_12 P_14 P_16 P_18 P_20 P_22 P_24 P_26 P_28 P_30 P_32
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32
RSTB\I SDC1FP\I IC1FP\I OCMP\I
20
14F9> 14C9> 14C9> 14F9>
B
4 47 1 47 2 47
MON
HEADER 16X2 CONN_MALE
4 1 2 3 4 5 8 7 6 5
Y7
0.1UF C178 4 2
50PPM OSC_EP26 3.3V VCC OUTPUT GND TS/PD
12 11 3
OEB INB GNDA GNDB GNDQ
RN223 RN225 RN225 RN225 RN225
47 47 47 47 47
7 8 9 10 11
R44
330
R608
1
MON
13
44.736MHZ A
R612
330
330
330
TP28 T DS3_CLK
5 16 8
R46
PMC-Sierra, Inc.
DOCUMENT NUMBER: PMC-2001170 DOCUMENT ISSUE NUMBER: 1 TITLE: OC-12 LINE CARD CLOCK BUFFERS ENGINEER: PMC-SIERRA (HS) ISSUE DATE: 2001/03/15 REVISION NUMBER: 1 PAGE:15 1 OF 19 A
10
9
8
7
6
5
4
3
2
10
9
8
7
6
5
4
3
2
1
REVISIONS
NOTE: VCC = 5V H 3.3 V PCI_VCC_5V
16D10>
ZONE
REV
DESCRIPTION
DATE
APPR
3.3 V 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K H
VIO_LONG PQFP U3
133 117 162 100 85 70 56 45 32 14 1 53 2 3 1 3 1 3 4 1 2 3 4 2 4 2 4 1 2 3
PCI_VCC_3.3V RN17 RN17 RN28 RN28 RN29 RN29 RN29 RN30 RN30 RN30 RN30 RN31 RN31 RN32 RN32 RN33 RN33 RN33 LA23 LA22 LA21 LA20 LA19 LA18 LA17 LA16 LA15 LA14 LA13 LA12 LA11 LA10 LA9 LA8 LA7 LA6 LA5 LA4 LA3 LA2 LAD31 LAD30 LAD29 LAD28 LAD27 LAD26 LAD25 LAD24 LAD23 LAD22 LAD21 LAD20 LAD19 LAD18 LAD17 LAD16 LAD15 LAD14 LAD13 LAD12 LAD11 LAD10 LAD9 LAD8 LAD7 LAD6 LAD5 LAD4 LAD3 LAD2 LAD1 LAD0
131 130 129 128 127 125 124 123 121 120 119 118 116 115 114 111 110 109 108 107 106 105 61 62 63 64 65 67 68 69 72 73 74 77 79 80 81 82 83 84 86 87 89 90 91 92 93 95 96 97 98 99 102 104 94 134 135 136 137 157 156 155 154 148 147 54 71 47.0 75 103 138 126 144 139 52 145 150 153 152 151 149 142 76 141 140 143 55 58 59 60 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
17F10< 17H10<
5V_PCI 3_3V_PCI
G
4.7K 4.7K R4 R5
J1
1 0 A24 B24 C24 D24 E24 A22 B22 C22 D22 E22 A20 B20 C20 D20 E20 A18 B18 C18 D18 E18 A16 B16 C16 D16 E16 18 17 16 A11 B11 C11 D11 E11 A9 B9 C9 D9 E9 A7 B7 C7 D7 E7 A5 B5 C5 D5 E5 A3 B3 C3 D3 E3 A1 B1 C1 D1 E1 F15 F17 F19 F21 F23 F25
A24 B24 C24 D24 E24 A22 B22 C22 D22 E22 A20 B20 C20 D20 E20 A18 B18 C18 D18 E18 A16 B16 C16 D16 E16
A25 B25 C25 D25 E25 A23 B23 C23 D23 E23 A21 B21 C21 D21 E21 A19 B19 C19 D19 E19 A17 B17 C17 D17 E17
A25 B25 C25 D25 E25 A23 B23 C23 D23 E23 A21 B21 C21 D21 E21 A19 B19 C19 D19 E19 A17 B17 C17 D17 E17 A15 B15 C15 D15 E15 A10 B10 C10 D10 E10 A8 B8 C8 D8 E8 A6 B6 C6 D6 E6 A4 B4 C4 D4 E4 21 20 19 26 25 24
P_ENUMB
16E7<
7 6 5
4 3 2
F
12 11 10
P_CBE0B 3.3 V
4.7K 15 14 13 R6
16E7<
16E7< 16E7< 16E7< 16E7< 16E7> 16E7>
P_SERRB P_PAR P_CBE1B P_DEVSELB P_STOPB P_LOCKB
169 4.7K R7 4.7K R8
PME
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
RN61 RN61 RN54 RN54 RN54 RN43 RN43 RN43 RN39 RN39 RN39 RN67 RN67 RN44 RN44 RN114
3 4 2 3 4 1 2 3 1 2 4 3 4 3 4 1
9 8
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
RN1 RN1 RN1 RN1 RN2 RN2 RN2 RN2 RN3 RN3 RN3 RN3 RN4 RN4 RN4 RN4 RN5 RN5 RN5 RN5 RN6 RN6 RN6 RN6 RN7 RN7 RN7 RN7 RN8 RN8 RN8 RN8
1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4
8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5
10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10
173 174 175 2 3 4 5 6 9 10 11 12 15 16 17 18 30 33 34 35 36 37 38 39 41 42 43 46 47 48 49 50
AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
VDD0 VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10
PCI_BUS<31..0>
V_I/O
7 6 8 6 8 6 5 8 7 6 5 7 5 7 5 8 7 6
ADDR_P<17..0>\I RN41 RN94 RN94 RN94 RN42 RN195 RN66 RN66 RN66 RN156 RN156 RN156 RN51 RN51 RN59 RN60 RN53 RN50
4 1 2 3 4 1 1 2 3 2 3 4 1 2 4 2 3 3 5 8 7 6 5 8 8 7 6 7 6 5 8 7 5 7 6 6
14G4<
22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
G
3.3 V
16E10> 16E10> 16E10> 16F8> 16E7> 16E10> 16G8> 16E8> 16E10< 16E10< 16E10> 16D8> 16E8> 16D10> 16F10> 16E10< 16D10< 16E8> 16E8>
P_CBE3B P_CBE2B P_CBE1B P_CBE0B P_DEVSELB P_ENUMB P_FRAMEB P_IDSEL P_LOCKB P_PAR P_PCLK P_PERRB P_RSTB P_SERRB P_STOPB P_INTAB P_IRDYB P_TRDYB
RN9 RN9 RN9 RN10 RN10 RN10 RN10 RN11 RN11 RN11 RN11 RN12 RN12 RN12 RN12 RN13 RN13
2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2
7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7
10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10
7 19 29 40 23 51 20 8 25 28 172 26 171 27 24 170 21 22
C/BE3 C/BE2 C/BE1 C/BE0 DEVSEL ENUM FRAME IDSEL LOCK PAR PCLK PERR RST SERR STOP INTA IRDY TRDY
E
P_PERRB
PCI9030-PQFP
16E7< 17D10< 16D7< 16E7< 16E7>
P_CBE2B BD_SELB P_CBE3B P_IDSEL
23 22
RN17 RN28 RN28 RN29
RN31 RN31 RN32 RN32
17E10< 16D10< 16C1< 16H6< 16D7<
VIO_LONG
0.1UF C1 30 29 28 27
1.2K
D
R14
A7 B7 C7 D7 E7 A5 B5 C5 D5 E5 A3 B3 C3 D3 E3 A1 B1 C1 D1 E1 F15 F17 F19 F21 F23 F25
A8 B8 C8 D8 E8 A6 B6 C6 D6 E6 A4 B4 C4 D4 E4 A2 B2 C2 D2 E2
16D10>
VIO_LONG
RN27 RN27
1 2
8 7
33 33
RN33 RN34 RN34
----A15 A11 B15 B11 C15 C11 D11 D15 E11 E15 ----A9 A10 B9 B10 C9 C10 D9 D10 E9 E10 --------
P_FRAMEB P_IRDYB P_TRDYB
16E7< 16E7< 16D7<
4 2 4 2
1 3 1 3
GPIO8 GPIO7/LA24 GPIO6/LA25 GPIO5/LA26 GPIO4/LA27 GPIO3/CS3* GPIO2/CS2* GPIO1/LLOCK0* GOIO0/WAIT0* CS1 CS0 CPCISW BCLKO ALE LPMRESET ADS LPMINT BTERM BLAST LED_ON LCLK LGNT LINTI2 LINTI1 LREQ LRESETO LW/R* MODE RD WR READY LBE3 LBE2 LBE1 LBE0
4 1 2
RN196 1 RN196 2 RN193 4 RN14 1 RN14 2 RN14 3 RN14 4 RN15 1 RN15 2 RN15 3 RN15 4 RN16 1 RN16 2 RN16 3 RN16 4 RN17 1 RN50 4 RN203 1 RN203 2 RN207 2 RN207 3 RN207 4 RN18 1 RN18 2 RN18 3 RN18 4 RN19 1 RN19 2 RN19 3 RN19 4 RN20 1 RN20 2
8 4.7K 7 4.7K 5 4.7K 8 4.7K 7 4.7K 6 4.7K 5 4.7K 8 4.7K 7 4.7K 6 4.7K 5 4.7K 8 4.7K 7 4.7K 6 4.7K 5 4.7K 8 4.7K 5 22 8 22 7 22 7 22 6 22 5 22 8 22 7 22 6 22 5 22 8 22 7 22 6 22 5 22 8 22 7 22
6 5 7 6 5 8 7 6 8 7 5 6 5 6 5 8
4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K
3.3 V
F
DATA_P<15..0>\I
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
14H4<>
3.3 V
4.7K 4.7K 4.7K 4.7K
4.7K 4.7K 4.7K 4.7K
5 7 5 7
8 6 8 6
5 8 7
4.7K 4.7K 4.7K
E
SBS_CSB_P\I CPLD_CSB_P\I
14E5< 14E5<
16E10>
BD_SELB 3.3 V
8 R16
RN27 RN27
R15
3 4
6 5
33 33 CPCISW
16A7>
TEMUX_IN_CSB_P\I SPECTRA_CSB_P\I
D
14E5< 14E5<
16E7< 16D10> 16E7> 17E10<
P_RSTB VIO_LONG P_INTAB 5V_LONG
100K R10
P_PCLK
31
16E7<
RN61
3.3 V DIP8_SOCKET U2
NM93CS56
4.7K A2 B2 C2 D2 E2 F1 F3 F5 F7 F9 F11 F13 0.1UF R9 C179 4.7K R11 8 7 6 5
10
4.7K
112
BD_SEL*/TEST
1
BLUE
2
220 R47
VIO_LONG
14E5< 14E5> 17D6<
16D10>
1
LCLK_P\I OUTPUT_INTB_P\I L_RSTB
VCC PRE PE GND
CS SK DI DO
1 2 3 4
158 161 159 160
EECS EEDI EEDO EESK
C
F1 F3 F5 F7 F9 F11 F13 ZPACK5X22A CPCI 2MM
17C3> 14A5> 13B5> 14A5< 19F2> 14A5>
TRSTB\I TCK\I TDO_SBS\I TDO_PROC\I TMS\I
C
164 165 168 167 166
TRST TCK TDI TDO TMS VSS0 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13
RDB_P\I WRB_P\I READYB_P\I 330 330 330
14F5< 14F5< 14E5>
176 163 146 132 122 113 101 88 78 66 57 44 31 13
TP30
TP31
TP32
TP33
RN187 RN187 RN187
2 3 4
7 6 5
B LBE0 T LBE1 T LBE2 T LBE3 T
B DRAWING ABBREV=PCI_INTERFACE TITLE=PCI_INTERFACE LAST_MODIFIED=Mon May 28 11:42:03 2001
P1
3.3 V STRIP3
3
1
2 10M 10M
HOLE_SIZE= 150MIL
MOUNTING HOLE
R13
HOT SWAP SWITCH STRIP2
R2 10M R1 R3
3.0K
DECOUPLING FOR PCI9030 PLACE ONE CAP FOR EACH VCC PIN.
3.3 V
CONN_2 J2 A1
2 1 3
PMC-Sierra, Inc.
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF C10 C11 0.1UF
CPCISW
16D3<
B1 C1
C2
C3
C4
C5
C6
C7
C8
C9
A
STRIP1
CPCI ESD STRIP
1 1.0K R12
C12
DOCUMENT NUMBER: PMC-2001170 DOCUMENT ISSUE NUMBER: 1 TITLE: OC-12 LINE CARD PCI_INTERFACE ENGINEER: PMC-SIERRA (HS)
ISSUE DATE: 2001/03/15 REVISION NUMBER: 1 PAGE:16 1 OF 19
A
10
9
8
7
6
5
4
3
2
10
9
8
7
6
5
4
3
2
1
REVISIONS
NOTE: VCC = 5V TPM H NOTE: THIS IS A BOARD VOUT
IRL3502S
1 2
3.3-1.8 BOARD U5
ZONE
REV
DESCRIPTION
DATE
APPR
CONTROL POWER SUPPLY TEST POINTS DISTRIBUTE THROUGOUT THE BOARD 1.8 V 1.8 V 3.3 V VCC H
GND
4
VIN
3
16G10>
3_3V_PCI
C17 4.7UF 0.1UF
2
3
Q5
1000UF
+
1
C15
TP51 +
1.0UF C22 1.0UF C25 100UF C21
T +5V T +5V T +5V
TP1 TP2 TP54
T +5V +5V T +5V T +5V
+
C27
TP52
1.0UF
10
R35
TP53
C29 0.01UF
0.022UF 2
C278
TP3 TP39 TP40 TP41 TP42 T +3_3V T +3_3V T +3_3V T +3_3V T +3_3V T +3_3V TP4 TP5 TP6 TP7 TP8 TP55 TP11
G SOD D3
1N4148W
.47
R40
C19 1.0M R36
NOTE: CONTROL PIN IS HANGING SO VOUT IS SET TO THE SPECIFIED DEVICE OUTPUT
T +3_3V T +3_3V T +3_3V T +3_3V T +3_3V T +3_3V T +3_3V T +1.8V +1_8V T +1.8V T +1.8V T +1.8V T +1.8V T +1.8V T +1.8V +3_3V
G
1
5.0-3.3 BOARD U7 VCC
4
TP43 TP44
CONTROL TPM NOTE: THIS IS A BOARD VOUT F
16G10>
1
GND
2
VIN
3
3.3 V
TP45 TP46
T +1.8V T +1.8V
TP12 TP15 TP16 TP19 TP23 TP56
5V_PCI
4.7UF 0.1UF
0.01 R31 0.01 C14 R32
IRL3502S
2 1 3
F
1000UF
Q4
TP47 T +1.8V
1.0UF C23 1.0UF C26 100UF C20 C28 1.0UF
C13
+
TP48 T +1.8V
C30
+
+
TP49 T +1.8V
0.01UF C279
10
R33
TP50 T +1.8V
.47
R63
3_3V_PCI
TP24
T 3_3V_PCI E T 5V_PCI
1.0K
0.1UF
E
16D10>
R34
VIO_LONG
C24
0 R24
5V_PCI
TP25
16C10>
5V_LONG
0 R25 8 7 6 6.81K R37
TP34
4.7K
T GND T GND T GND T GND T GND T GND D T GND T GND T GND T GND T GND T GND GND
U4
R30
3.3 V
R111 R112 R43
3.3 V
3.3 V
TP35 TP36
SENSE
GATE
VCC
4.7K
4.7K
2 4.7K R26
ON
4.7K
4.7K
4.7K
TIMER
FB LTC1422 SOIC RESET GND
5
4.7K
R41
R119
R39
TP37 TP57 TP58
TC74LVX08FN
U6
1 1 3 2 0.047UF
TC74LVX08FN
U6
9 8 10
D
3
RSTB_IN\I
14E5< 17A8<
TP59 TP60
0.33UF 3
C18
4
16E10>
BD_SELB
1 2
2.43K R38
4.7K R28
MMBT3904 C16
3.3 V
10UF
SW1 VERT_6MM
2
PBNO
TP61
C181
+
U6
16C1> 19C5>
4.7K
R142
TC74LVX08FN
TP62 TP63
L_RSTB RSTBN\I
4 6 5 12
TC74LVX08FN
U6
11
1
TRSTB\I
14E5> 14A5>
TRSTB_IN\I
13
3A10< 5H9< 6H9< 7H10< 8H10< 13B5< 16C7< 19F2<
TP64
C
C
VCC
1.8 V
3.3 V
33UF
33UF
33UF
33UF
33UF
C188
C183
C189
C214
C215
33UF
33UF
33UF
33UF
33UF
C180
C182
C184
C185
C186
33UF
33UF
POWER / RESET INDICATORS
VCC 3.3 V 1.8 V
C187
C216
+
+
+
+
+
+
+
+
+
+
+
+
B
B DRAWING PCI_INTERFACE PCI_INTERFACE LAST_MODIFIED=Mon May 28 11:42:08 2001
3 1.0K R21 2 1
MMBT3904
SOT23
PMC-Sierra, Inc.
DOCUMENT NUMBER: PMC-2001170 DOCUMENT ISSUE NUMBER: 1 ISSUE DATE: 2001/03/15 REVISION NUMBER: 1 PAGE:17 1 OF 19 A
A
150 150 270 150 R20 R421 R17 R422 A1 A2 A3 A4
GREEN D2
K1 K2 K3 K4
RSTB_IN\I
17D3>
~20MA ->
LED SSF-LXH5147
TITLE: OC-12 LINE CARD POWER SUPPLY / HOT SWAP CONTROL ENGINEER: PMC-SIERRA (HS)
10
9
8
7
6
5
4
3
2
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
NOTE: ALL LVDS LINES ARE 50 OHMS
15B3< 14B9<
BP_CMP\I RWSEL\I G
G
13A10<
13F4< 13F4<
RNPROT\I RPPROT\I
50 OHM 50 OHM
PROTECTION LINK
F
13F4> 13F4>
TPPROT\I TNPROT\I 50 OHM
50 OHM
F
J14
AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10
J14
J14
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10
J14
D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10
15F4> 15B3< 14B9<
BP_77MOUT\I BP_77M\I
E
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10
A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6 B6 A7 B7 A8 B8 A9 B9 A10 B10 AMP_HS3_6X10 FEMALE_RA_1
C1 D1 C2 D2 C3 D3 C4 D4 C5 D5 C6 D6 C7 D7 C8 D8 C9 D9 C10 D10 AMP_HS3_6X10 FEMALE_RA_1
E1 F1 E2 F2 E3 F3 E4 F4 E5 F5 E6 F6 E7 F7 E8 F8 E9 F9 E10 F10 AMP_HS3_6X10 FEMALE_RA_1
F1 F2 F3 F4 F5 F6 F7 F8 F9 F10
AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AMP_HS3_6X10 FEMALE_RA_1 J14
E
CD1 CD2 CD3 CD4 CD5 CD6 CD7 CD8 CD9 CD10
13G4< 13G4<
RPWRK\I RNWRK\I
50 OHM 50 OHM
CD1 CD2 CD3 CD4 CD5 CD6 CD7 CD8 CD9 CD10 AMP_HS3_6X10 FEMALE_RA_1 J14
D
WORKING LINK
EF1 EF2 EF3 EF4 EF5 EF6 EF7 EF8 EF9 EF10
EF1 EF2 EF3 EF4 EF5 EF6 EF7 EF8 EF9 EF10 AMP_HS3_6X10 FEMALE_RA_1
D
13F4> 13F4>
TNWRK\I TPWRK\I
50 OHM 50 OHM C
C
15B3< 14B9< 14C9>
BP_FP\I FPOUT\I
B
B
PMC-Sierra, Inc.
A DOCUMENT NUMBER: PMC-2001170 DOCUMENT ISSUE NUMBER: 1 TITLE: OC-12 LINE CARD LVDS_INTERFACE ENGINEER: PMC-SIERRA INC (HS) 10 9 8 7 6 5 4 3 2 ISSUE DATE: 2001/03/15 REVISION NUMBER: 1 PAGE:18 1 OF 19 A
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
J6 3P MOLEX_7MM
J? TX+ TXRX+ RX2 4 1 3 42 41 44 43 46 45 48 49 51 50 53 94 93 10 9 100 99 104 101 106 103 108 105 112 113 114 115 116 117 120 119 131 138 133 140 135 142 137 144 146 143 148 145 150 147 152 149 77 81 80 83 82 85 84 87 121 124 126 139 134 122 110 123 98 97 89 151 132 111 90 71 52 29 19 17 15 154 141 136 125 118 107 102 96 95 92 91 86 79 72 63 56 47 40 31 26 8 7
UNIVERSAL J7 22 2 22 3 22 4 22 1
7 6 5 8
3.3 V 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K
6 8 6 8 6 8 6 8 6 8 6 8 6 8 6 8 7 6
RN119 RN119 RN119 RN136
G
GPIO_20 GPIO_19 GPIO_18 GPIO_17 GPIO_16 GPIO_15 GPIO_14 GPIO_13 GPIO_12 GPIO_11 GPIO_10 CLOCK2 CLOCK1 MRST NRST
1 2 3 4 5 6 7 8 11 12
1 2 3 4 5 6 7 8
SHIELD1 SHIELD2
G
13 14 3 1 3 1 3 1 3 1 3 1 3 1 3 1 3 1 2 3
RJ45_SHIELD
RN114 RN115 RN115 RN141 RN141 RN142 RN142 RN189 RN189 RN190 RN190 RN191 RN191 RN192 RN192 RN193 RN193 RN193
ADDRN<17..0>\I LCLKN\I
J6 MOLEX_7MM 101P
14D4<
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
J?
14C5>
3.3 V 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K
USB+ USBTCK TRST TDO TDI TMS L_DD7 L_DD6 L_DD5 L_DD4 L_DD3 L_DD2 L_DD1 L_DD0
12 11 14 16 18 20 22 67 70 69 74 73 76 75 78 64 66 68 65 24 23 25 27 33 35 34 32 30 28 160 158 156 159 157 155 153 130 129 128 127 109 88 21 6 5 13 36 37 38 39 55 54 57 58 59 60 61 62 MH2 MH1 4.7K R64 1 2 3 4 5 6 7 8 9
F
E
AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 A7 A6 A5 A4 A3 A2 A1 A0 ALE# RD# WE# WE0# WE1# WE2# WE3# RDY# CS0# CS1# URST# VCC10 VCC9 VCC8 VCC7 VCC6 VCC5 VCC4 VCC3 VCC2 VCC1 GND22 GND21 GND20 GND19 GND18 GND17 GND16 GND15 GND14 GND13 GND12 GND11 GND10 GND9 GND8 GND7 GND6 GND5 GND4 GND3 GND2 GND1
TCK\I TRSTB\I TDO_PROC\I TDO_SBS\I TMS\I
14A5> 17C3> 16C7> 14A5< 13B5> 14A5>
F
RN20 RN20 RN21 RN21 RN21 RN21 RN22 RN22 RN22 RN22
3 4 1 2 3 4 1 2 3 4
6 5 8 7 6 5 8 7 6 5
22 22 22 22 22 22 22 22 22 22
17 16 15 14 13 12 11 10 9 8
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
RN114 2 RN114 4 RN115 2 RN115 4 RN141 2 RN141 4 RN142 2 RN142 4 RN189 2 RN189 4 RN190 2 RN190 4 RN191 2 RN191 4 RN192 2 RN192 4
7 5 7 5 7 5 7 5 7 5 7 5 7 5 7 5
DATAN<15..0>\I RN25 1 RN25 2 RN25 3 RN25 4 RN40 1 RN40 2 RN40 3 RN40 4 RN79 1 RN79 2 RN79 3 RN79 4 RN120 1 RN120 2 RN120 3 RN120 4
8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5
22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
14E4<>
L_PCLK L_BIAS L_LCLK L_FCLK PKTSEL NPOE NPWE NPIOR NPIOW NPCE_1 NIOIS16 NPWAIT NPREG NPCE_2 RSTX3 RSTX2 RSTX1 RSRX3 RSRX2 RSRX1 WP RSVD9 RSVD8 RSVD7 RSVD6 RSVD5 RSVD4 RSVD3 RSVD2 RSVD1 BFAULT XSDO XSFRAME XSDI XSCLK LCD_D15 LCD_D14 LCD_D13 LCD_D12 LCD_D11 LCD_D10 LCD_D9 LCD_D8 MH2 MH1 2 OF 2
3.3 V 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K
E
6 5 8 7 6 5 8
FEMALE J8 DCD RXD TXD DTR GND DSR RTS CTS RI D
MICROPROCESSOR
MICROPROCESSOR
RN23 RN23 RN23 RN23 RN24 RN24 RN24 RN24
1 2 3 4 1 2 3 4
8 7 6 5 8 7 6 5
22 22 22 22 22 22 22 22
7 6 5 4 3 2 1 0
3 4 1 2 3 4 1
RN34 RN34 RN35 RN35 RN35 RN35 RN36
3.3 V
OUTPUT_INTBN\I
14C5>
D
RDBN\I WRBN\I
DB9_FEMALE
14C5< 14C5<
READYBN\I CSB_0N\I CSB_1N\I RSTBN\I
14C5> 14C5< 14C5< 17C6<
3.3 V
C
C
B
B
1 OF 2
PMC-Sierra, Inc.
A DOCUMENT NUMBER: PMC-2001170 DOCUMENT ISSUE NUMBER: 1 TITLE: OC-12 LINE CARD PROCESSOR_INTERFCACE ENGINEER: PMC-SIERRA INC (HS) 10 9 8 7 6 5 4 3 2 ISSUE DATE: 2001/03/15 REVISION NUMBER: 1 PAGE:19 1 OF 19 A
PRELIMINARY REFERENCE DESIGN PMC - 2001170 ISSUE 1
PM8316 TEMUX-84 PM8611 SBS-LITE
OC-12 LINE CARD REFERENCE DESIGN
NOTES
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
85
PRELIMINARY REFERENCE DESIGN PMC - 2001170 ISSUE 1
PM8316 TEMUX-84 PM8611 SBS-LITE
OC-12 LINE CARD REFERENCE DESIGN
CONTACTING PMC-SIERRA, INC. PMC-Sierra, Inc. 105-8555 Baxter Place Burnaby, BC Canada V5A 4V7 Tel: Fax: (604) 415-6000 (604) 415-6200 document@pmc-sierra.com info@pmc-sierra.com apps@pmc-sierra.com http://www.pmc-sierra.com
Document Information: Corporate Information: Application Information: Web Site:
None of the information contained in this document constitutes an express or implied warranty by PMC-Sierra, Inc. as to the sufficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchantability, performance, compatibility with other parts or systems, of any of the products of PMC-Sierra, Inc., or any portion thereof, referred to in this document. PMC-Sierra, Inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not limited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement. In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the information, whether or not PMC-Sierra, Inc. has been advised of the possibility of such damage. (c) 2001 PMC-Sierra, Inc. PMC-2001170 (P1) Issue date: June 2001
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE

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